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Revision 164

Added by markw about 11 years ago

It is important when we sample and when we toggle. Fixes "clarinet".

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common/a8core/pokey.vhdl
component pokey_noise_filter IS
PORT
(
CLK : IN STD_LOGIC;
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
......
-- Instantiate audio noise filters
pokey_noise_filter0 : pokey_noise_filter
port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
port map(clk=>clk,noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter1 : pokey_noise_filter
port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
port map(clk=>clk,noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter2 : pokey_noise_filter
port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
port map(clk=>clk,noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter3 : pokey_noise_filter
port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
port map(clk=>clk,noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
-- Audio output stage
process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
begin
chan0_output_next <= chan0_output_reg;
chan1_output_next <= chan1_output_reg;
chan2_output_next <= chan2_output_reg;
chan3_output_next <= chan3_output_reg;
if (audf0_pulse_noise = '1') then
chan0_output_next <= not(chan0_output_reg);
end if;
if (audf1_pulse_noise = '1') then
chan1_output_next <= not(chan1_output_reg);
end if;
if (audf2_pulse_noise = '1') then
chan2_output_next <= not(chan2_output_reg);
end if;
if (audf3_pulse_noise = '1') then
chan3_output_next <= not(chan3_output_reg);
end if;
end process;
-- (toggling now handled in the noise filter - the subtlety on when to toggle and when to sample is important)
chan0_output_next <= audf0_pulse_noise;
chan1_output_next <= audf1_pulse_noise;
chan2_output_next <= audf2_pulse_noise;
chan3_output_next <= audf3_pulse_noise;
-- High pass filters
process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
common/a8core/pokey_noise_filter.vhdl
ENTITY pokey_noise_filter IS
PORT
(
CLK : IN STD_LOGIC;
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
......
END pokey_noise_filter;
ARCHITECTURE vhdl OF pokey_noise_filter IS
signal pulse_noise_a : std_logic;
signal pulse_noise_b : std_logic;
-- signal pulse_noise_a : std_logic;
-- signal pulse_noise_b : std_logic;
signal audclk : std_logic;
signal out_next : std_logic;
signal out_reg : std_logic;
BEGIN
process(pulse_in, noise_4, noise_5, noise_large, pulse_noise_a, pulse_noise_b, noise_select)
process(clk)
begin
pulse_noise_a <= noise_large;
pulse_noise_b <= noise_5 and pulse_in;
if (NOISE_SELECT(1) = '1') then
pulse_noise_a <= noise_4;
if (clk'event and clk='1') then
out_reg <= out_next;
end if;
if (NOISE_SELECT(2) = '1') then
pulse_noise_b <= pulse_in;
end process;
pulse_out <= out_reg;
process(pulse_in, noise_4, noise_5, noise_large, noise_select, audclk, out_reg)
begin
audclk <= pulse_in;
out_next <= out_reg;
if (NOISE_SELECT(2) = '0') then
audclk <= pulse_in and noise_5;
end if;
PULSE_OUT <= pulse_noise_a and pulse_noise_b;
if (NOISE_SELECT(0) = '1') then
PULSE_OUT <= pulse_noise_b;
end if;
if (audclk = '1') then
if (NOISE_SELECT(0) = '1') then
-- toggle
out_next <= not(out_reg);
else
-- sample
if (NOISE_SELECT(1) = '1') then
out_next <= noise_4;
else
out_next <= noise_large;
end if;
end if;
end if;
end process;
end vhdl;
end vhdl;

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