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Revision 1545

Added by markw 5 days ago

Allow recording of a channel to the sample memory (for looping etc). Allow feeding a channel to the SID ext input, in order to use filters. This mutes the original channel so its not duplicated..

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atari_chips/pokeyv2/mixer.vhdl
B_CH0 : IN SIGNED(15 downto 0);
B_CH1 : IN SIGNED(15 downto 0);
MUTE_CHANNEL : IN STD_LOGIC;
S_AUDIO : OUT SIGNED(15 downto 0);
S_LEFT : OUT STD_LOGIC;
S_RIGHT : OUT STD_LOGIC;
S_CHANNEL : OUT UNSIGNED(2 downto 0);
AUDIO_0_SIGNED : out signed(15 downto 0);
AUDIO_1_SIGNED : out signed(15 downto 0);
AUDIO_2_SIGNED : out signed(15 downto 0);
......
signal left_on_right : std_logic;
signal volume : signed(15 downto 0);
signal out_left_enable : std_logic;
signal out_right_enable : std_logic;
signal saturated : signed(15 downto 0);
signal write : std_logic;
......
process(state_reg,RIGHT_REG,RIGHT_SNAP_REG,RIGHT_SNAP_NEXT,out_ch_reg,acc_reg,volume,dc_reg,dc_corrected_reg,
POST_DIVIDE,SATURATED,include_in_output,enable_cycle)
POST_DIVIDE,SATURATED,include_in_output,enable_cycle,mute_channel)
variable postdivide : std_logic_vector(1 downto 0);
variable presaturate : signed(19 downto 0);
variable addAcc : std_logic;
......
-- Accumulator update: clear takes priority over add
if clearAcc = '1' then
acc_next <= (others=>'0');
elsif addAcc = '1' then
elsif addAcc = '1' and mute_channel='0' then
acc_next <= acc_reg + resize(volume, 20);
end if;
......
)
begin
volume <= (others=>'0');
out_left_enable <= channelsel(3);
out_right_enable <= not(channelsel(3));
--left
include_in_output(0) <= not(channelsel(3));
include_in_output(2) <= not(channelsel(3));
......
when x"6"|x"e" =>
include_in_output <= B_CH0_EN;
volume <= B_CH0;
out_left_enable <= '1';
out_right_enable <= '1';
when x"7"|x"f" =>
include_in_output <= B_CH1_EN;
volume <= B_CH1;
out_left_enable <= '1';
out_right_enable <= '1';
when others =>
out_left_enable <= '0';
out_right_enable <= '0';
end case;
end process;
......
end process;
-- output
S_AUDIO <= VOLUME;
S_LEFT <= out_left_enable;
S_RIGHT <= out_right_enable;
S_CHANNEL <= unsigned(CHANNELSEL(2 downto 0));
AUDIO_0_SIGNED <= audio0_reg;
AUDIO_1_SIGNED <= audio1_reg;
AUDIO_2_SIGNED <= audio2_reg;
atari_chips/pokeyv2/pokeymax.vhd
-- SID
signal SID_CLK_ENABLE : std_logic;
signal SID_AUDIO_SIGNED : SIGNED_AUDIO_TYPE(1 downto 0);
signal SID_AUDIO_IN_SIGNED : SIGNED_AUDIO_TYPE(1 downto 0);
signal SID_FLASH1_ADDR : std_logic_vector(16 downto 0);
signal SID_FLASH1_ROMREQUEST : std_logic;
signal SID_FLASH1_ROMREADY : std_logic;
signal SID_FLASH2_ADDR : std_logic_vector(16 downto 0);
signal SID_FLASH2_ROMREQUEST : std_logic;
signal SID_FLASH2_ROMREADY : std_logic;
signal SID_FILTER1_REG : std_logic_vector(1 downto 0);
signal SID_FILTER1_NEXT : std_logic_vector(1 downto 0);
signal SID_FILTER2_REG : std_logic_vector(1 downto 0);
signal SID_FILTER2_NEXT : std_logic_vector(1 downto 0);
signal SID_FILTER1_REG : std_logic_vector(2 downto 0);
signal SID_FILTER1_NEXT : std_logic_vector(2 downto 0);
signal SID_FILTER2_REG : std_logic_vector(2 downto 0);
signal SID_FILTER2_NEXT : std_logic_vector(2 downto 0);
signal SID1_FILTER_BP : signed(17 downto 8);
signal SID1_FILTER_HP : signed(17 downto 8);
signal SID1_F_RAW : std_logic_vector(12 downto 0);
......
-- SAMPLE/COVOX
signal SAMPLE_AUDIO_SIGNED : SIGNED_AUDIO_TYPE(1 downto 0);
signal SAMPLE_AUDIO_IN_SIGNED : SIGNED_AUDIO_TYPE(1 downto 0);
signal SAMPLE_IRQ : std_logic;
signal SAMPLE_RAM_ADDRESS : std_logic_vector(15 downto 0);
signal SAMPLE_RAM_WRITE_ENABLE : std_logic;
signal SAMPLE_RAM_DATA : std_logic_vector(7 downto 0);
signal SAMPLE_RAM_READ_DATA : std_logic_vector(7 downto 0);
signal SAMPLE_RAM_WRITE_DATA : std_logic_vector(7 downto 0);
signal ADPCM_STEP_ADDR : std_logic_vector(6 downto 0);
signal ADPCM_STEP_REQUEST : std_logic;
signal ADPCM_STEP_READY : std_logic;
-- MIXER
signal mixer_audio_out : signed(15 downto 0);
signal mixer_l_enable : std_logic;
signal mixer_r_enable : std_logic;
signal mixer_audio_out_channel : unsigned(2 downto 0);
signal mixer_mute : std_logic;
signal MIXER_SIGNED_REG : SIGNED_AUDIO_TYPE(1 downto 0);
signal MIXER_SIGNED_NEXT : SIGNED_AUDIO_TYPE(1 downto 0);
signal MIX_SEL_NEXT : std_logic_vector(4 downto 0);
signal MIX_SEL_REG : std_logic_vector(4 downto 0);
-- FLASH
signal flash_do_slow : std_logic_vector(31 downto 0); --58Mhz
......
AUDIO => SID_AUDIO_SIGNED(0),
SIDTYPE => SID_FILTER1_REG(0),
EXT => "0"&SID_FILTER1_REG(1),
EXT_ADC => (others=>'0'),
EXT => SID_FILTER1_REG(2 downto 1),
EXT_ADC => signed_to_unsigned(SID_AUDIO_IN_SIGNED(0)),
POT_X => '0',
POT_Y => '0',
......
AUDIO => SID_AUDIO_SIGNED(1),
SIDTYPE => SID_FILTER2_REG(0),
EXT => "0"&SID_FILTER2_REG(1),
EXT_ADC => (others=>'0'),
EXT => SID_FILTER2_REG(2 downto 1),
EXT_ADC => signed_to_unsigned(SID_AUDIO_IN_SIGNED(1)),
POT_X => '0',
POT_Y => '0',
......
AUDIO0 => SAMPLE_AUDIO_SIGNED(0),
AUDIO1 => SAMPLE_AUDIO_SIGNED(1),
IRQ => SAMPLE_IRQ,
AUDIO_IN0 => SAMPLE_AUDIO_IN_SIGNED(0),
AUDIO_IN1 => SAMPLE_AUDIO_IN_SIGNED(1),
RAM_ADDR => SAMPLE_RAM_ADDRESS,
RAM_WRITE_ENABLE => SAMPLE_RAM_WRITE_ENABLE,
RAM_DATA => SAMPLE_RAM_DATA,
RAM_DATA => SAMPLE_RAM_READ_DATA,
RAM_WRITE_DATA => SAMPLE_RAM_WRITE_DATA,
ADPCM_STEP_ADDR => ADPCM_STEP_ADDR,
ADPCM_STEP_REQUEST => ADPCM_STEP_REQUEST,
......
(
clock => clk,
reset_n => reset_n,
data => write_data,
data => sample_ram_write_data,
address => sample_ram_address,
we => sample_ram_write_enable,
q => sample_ram_data
q => sample_ram_read_data
);
end generate;
......
(
clock => clk,
reset_n => reset_n,
data => write_data,
data => sample_ram_write_data,
address => sample_ram_address,
we => sample_ram_write_enable,
q => sample_ram_data
q => sample_ram_read_data
);
end generate;
......
(
clock => clk,
reset_n => reset_n,
data => write_data,
data => sample_ram_write_data,
address => sample_ram_address,
we => sample_ram_write_enable,
q => sample_ram_data
q => sample_ram_read_data
);
end generate;
......
PSG_STEREOMODE_REG <= "01"; --Polish
PSG_PROFILESEL_REG <= "00"; --Simple log
PSG_ENVELOPE16_REG <= '0'; --32 step
SID_FILTER1_REG <= "10"; -- 0=8580,1=6581,2=digifix
SID_FILTER2_REG <= "10"; -- 0=8580,1=6581,2=digifix
SID_FILTER1_REG <= "010"; -- 0=8580,1=6581,2=digifix
SID_FILTER2_REG <= "010"; -- 0=8580,1=6581,2=digifix
RESTRICT_CAPABILITY_REG <= (others=>'1');
CHANNEL_EN_REG <= (others=>'1');
MIXER_SIGNED_REG(0) <= to_signed(0,16);
MIXER_SIGNED_REG(1) <= to_signed(0,16);
MIX_SEL_REG <= (others=>'0');
elsif (clk'event and clk='1') then
DETECT_RIGHT_REG <= DETECT_RIGHT_NEXT;
IRQ_EN_REG <= IRQ_EN_NEXT;
......
SID_FILTER2_REG <= SID_FILTER2_NEXT;
RESTRICT_CAPABILITY_REG <= RESTRICT_CAPABILITY_NEXT;
CHANNEL_EN_REG <= CHANNEL_EN_NEXT;
MIXER_SIGNED_REG <= MIXER_SIGNED_NEXT;
MIX_SEL_REG <= MIX_SEL_NEXT;
end if;
end process;
......
CPU_FLASH_COMPLETE,CONFIG_FLASH_COMPLETE,CONFIG_FLASH_ADDR,flash_do_slow,
RESTRICT_CAPABILITY_REG,
CHANNEL_EN_REG,
PAL_REG
PAL_REG,
MIX_SEL_REG
)
begin
SATURATE_NEXT <= SATURATE_REG;
......
PAL_NEXT <= PAL_REG;
MIX_SEL_NEXT <= MIX_SEL_REG;
if (CPU_FLASH_COMPLETE='1') then
CPU_FLASH_DATA_NEXT <= flash_do_slow;
CPU_FLASH_REQUEST_NEXT <= '0';
......
PSG_PROFILESEL_NEXT <= flash_do_slow(30 downto 29);
-- 31 reserved
when "1" =>
SID_FILTER1_NEXT <= flash_do_slow(1 downto 0);
-- 2-3 reserved
SID_FILTER2_NEXT <= flash_do_slow(5 downto 4);
-- 6-7 reserved
SID_FILTER1_NEXT <= flash_do_slow(2 downto 0);
-- 3 reserved
SID_FILTER2_NEXT <= flash_do_slow(6 downto 4);
-- 7 reserved
RESTRICT_CAPABILITY_NEXT <= flash_do_slow(12 downto 8);
-- 13-15 reserved
-- 16-23 reserved (used in sidmax)
-- 21-23 reserved (used in sidmax)
MIX_SEL_NEXT(4 downto 0) <= flash_do_slow(20 downto 16); -- (clash with sidmix)
CHANNEL_EN_NEXT <= flash_do_slow(28 downto 24);
-- 29-31 reserved
when others =>
......
end if;
if (addr_decoded4(6)='1') then
SID_FILTER1_NEXT <= WRITE_DATA(1 downto 0);
SID_FILTER2_NEXT <= WRITE_DATA(5 downto 4);
-- (3 downto 1) reserved in case we want all revisions!
SID_FILTER1_NEXT <= WRITE_DATA(2 downto 0);
SID_FILTER2_NEXT <= WRITE_DATA(6 downto 4);
end if;
if (addr_decoded4(7)='1') then
RESTRICT_CAPABILITY_NEXT(4 downto 0) <= WRITE_DATA(4 downto 0);
end if;
if (addr_decoded4(8)='1') then
MIX_SEL_NEXT(4 downto 0) <= WRITE_DATA(4 downto 0);
end if;
if (addr_decoded4(9)='1') then
CHANNEL_EN_NEXT(4 downto 0) <= WRITE_DATA(4 downto 0);
end if;
......
CPU_FLASH_REQUEST_REG, CPU_FLASH_WRITE_N_REG,
RESTRICT_CAPABILITY_REG,
CHANNEL_EN_REG,
PAL_REG
PAL_REG,
MIX_SEL_REG
)
variable ACTUAL_CAPABILITY : std_logic_vector(7 downto 0);
begin
......
CONFIG_DO(6 downto 5) <= PSG_PROFILESEL_REG;
end if;
if (addr_decoded4(6)='1') then
if (addr_decoded4(6)='1') then -- different use on sidmax
CONFIG_DO <= (others=>'0');
CONFIG_DO(1 downto 0) <= SID_FILTER1_REG;
-- (3 downto 2) reserved in case we want more filter options
CONFIG_DO(5 downto 4) <= SID_FILTER2_REG;
-- (7 downto 6) reserved in case we want more filter options
CONFIG_DO(2 downto 0) <= SID_FILTER1_REG;
-- (3 downto 3) reserved in case we want more filter options
CONFIG_DO(6 downto 4) <= SID_FILTER2_REG;
-- (7 downto 7) reserved in case we want more filter options
end if;
if (addr_decoded4(7)='1') then
CONFIG_DO(4 downto 0) <= RESTRICT_CAPABILITY_REG(4 downto 0);
end if;
if (addr_decoded4(8)='1') then -- different use on sidmax
CONFIG_DO(4 downto 0) <= MIX_SEL_REG(4 downto 0);
end if;
if (addr_decoded4(9)='1') then
CONFIG_DO(4 downto 0) <= CHANNEL_EN_REG(4 downto 0);
end if;
......
R_CH4 => unsigned_to_signed(PSG_AUDIO_UNSIGNED(1)),
B_CH0 => GTIA_AUDIO_SIGNED,
B_CH1 => unsigned_to_signed(SIO_AUDIO_UNSIGNED),
MUTE_CHANNEL => mixer_mute,
S_AUDIO => mixer_audio_out,
S_LEFT => mixer_l_enable,
S_RIGHT => mixer_r_enable,
S_CHANNEL => mixer_audio_out_channel,
AUDIO_0_SIGNED => AUDIO_MIXED_SIGNED(0),
AUDIO_1_SIGNED => AUDIO_MIXED_SIGNED(1),
AUDIO_2_SIGNED => AUDIO_MIXED_SIGNED(2),
AUDIO_3_SIGNED => AUDIO_MIXED_SIGNED(3)
);
-- provide audio back to:
-- sample enggine -> to record to ram
-- sid ext -> to use filter (mutes original output)
-- S_AUDIO => mixer_audio_out,,
-- S_LEFT => mixer_l_enable,
-- S_RIGHT => mixer_r_enable,
-- S_CHANNEL => mixer_audio_out_channel,
process(MIXER_SIGNED_REG, mixer_l_enable, mixer_r_enable, mixer_audio_out, MIX_SEL_REG, mixer_audio_out_channel, SID_FILTER1_REG, SID_FILTER2_REG)
begin
MIXER_SIGNED_NEXT <= MIXER_SIGNED_REG;
mixer_mute <= '0';
if (std_logic_vector(mixer_audio_out_channel) = MIX_SEL_REG) then
if (mixer_l_enable='1') then
MIXER_SIGNED_NEXT(0) <= mixer_audio_out;
mixer_mute <= SID_FILTER1_REG(1);
end if;
if (mixer_r_enable='1') then
MIXER_SIGNED_NEXT(1) <= mixer_audio_out;
mixer_mute <= SID_FILTER2_REG(1);
end if;
end if;
end process;
SAMPLE_AUDIO_IN_SIGNED <= MIXER_SIGNED_REG;
SID_AUDIO_IN_SIGNED <= MIXER_SIGNED_REG;
-- sigma delta dither shared component (used in impl 4)
dac_dithergen : entity work.sigmadelta_dither
port map
(
......
spdif_out => spdif_out
);
EXT(SPDIF_BIT) <= spdif_out when CHANNEL_EN_REG(4)='1' else 'Z';
EXT(SPDIF_BIT) <= spdif_out when CHANNEL_EN_REG(4)='1' else 'Z'; -- TODO wrong clock domain
end generate spdif_on;
-- io extension
......
fir_off : if adc_fir_filter_v4=0 generate
adc_out_signed <= adc_in_signed;
FIR_DATA_REQUEST <= '0';
FIR_DATA_ADDRESS <= (others=>'0');
end generate fir_off;
SIO_AUDIO_UNSIGNED <= unsigned(not(adc_use_reg(15))&adc_use_reg(14 downto 0));
atari_chips/pokeyv2/sample/top.vhdl
AUDIO1 : out signed(15 downto 0);
IRQ : out std_logic;
AUDIO_IN0 : in signed(15 downto 0);
AUDIO_IN1 : in signed(15 downto 0);
RAM_ADDR : out std_logic_vector(15 downto 0);
RAM_WRITE_ENABLE : out std_logic;
RAM_DATA : in std_logic_vector(7 downto 0); -- next cycle: TODO, what if we use rom?
RAM_WRITE_DATA : out std_logic_vector(7 downto 0);
ADPCM_STEP_ADDR : out std_logic_vector(6 downto 0);
ADPCM_STEP_REQUEST : out std_logic;
......
signal ram_cpu_addr_reg : std_logic_vector(15 downto 0);
signal ram_cpu_write_enable : std_logic;
signal ram_record_write_enable : std_logic;
signal ram_record_enabled_reg : std_logic;
signal ram_record_enabled_next : std_logic;
signal ram_record_source_reg : std_logic;
signal ram_record_source_next : std_logic;
signal ch0_start_addr_reg : std_logic_vector(15 downto 0);
signal ch0_start_addr_next : std_logic_vector(15 downto 0);
signal ch0_len_reg : std_logic_vector(15 downto 0);
......
dma_on_reg,dma_on,ram_data,
channel_reg,
irq_en_reg,irq_active_reg,irq_trigger,irq_clear_n,
adpcm_reg, bits8_reg
adpcm_reg, bits8_reg,
ram_record_enabled_reg, ram_record_source_reg
)
begin
ram_cpu_write_enable <= '0';
......
adpcm_next <= adpcm_reg;
ram_record_enabled_next <= ram_record_enabled_reg;
ram_record_source_next <= ram_record_source_reg;
if (write_enable='1') then
if (addr_decoded5(4)='1') then
ram_cpu_addr_next(7 downto 0) <= DI;
......
adpcm_next <= DI(3 downto 0);
bits8_next <= DI(7 downto 4);
end if;
if (addr_decoded5(20)='1') then
ram_record_enabled_next <= DI(0);
ram_record_source_next <= DI(1);
end if;
end if;
end process;
......
dma_on_reg,
adpcm_reg,
bits8_reg,
adpcm_data_request)
adpcm_data_request,
ram_record_source_reg, ram_record_enabled_reg)
begin
ram_addr <= (others=>'0');
data_nibble <= '0';
adpcm_on <= '0';
dma_on <= '0';
bits8 <= '0';
ram_record_write_enable <='0';
adpcm_data_ready_next <= adpcm_data_request;
......
adpcm_on <= adpcm_reg(0);
dma_on <= dma_on_reg(0);
bits8 <= bits8_reg(0);
if (ram_record_enabled_reg ='1') then
ram_record_write_enable <= '1';
end if;
when "01" =>
ram_addr <= ch1_addr(16 downto 1);
data_nibble <= ch1_addr(0);
......
adpcm_data_ready_reg <= '0';
bits8_reg <= (others=>'1');
ram_record_enabled_reg <= '0';
ram_record_source_reg <= '0';
elsif (clk'event and clk='1') then
CH0_REG <= CH0_NEXT;
......
adpcm_data_ready_reg <= adpcm_data_ready_next;
bits8_reg <= bits8_next;
ram_record_enabled_reg <= ram_record_enabled_next;
ram_record_source_reg <= ram_record_source_next;
end if;
end process;
IRQ <= or_reduce(irq_active_reg);
RAM_WRITE_ENABLE <= RAM_CPU_WRITE_ENABLE;
RAM_WRITE_ENABLE <= RAM_CPU_WRITE_ENABLE OR RAM_RECORD_WRITE_ENABLE;
RAM_WRITE_DATA <= std_logic_vector(AUDIO_IN1(15 downto 8)) when ram_record_source_reg='1' else std_logic_vector(AUDIO_IN0(15 downto 8));
END vhdl;

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