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Revision 1538
Added by markw 1 day ago
| atari_chips/pokeyv2/pll_reset_sync.vhdl | ||
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pll_reset_sync is
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generic (
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| ... | ... | |
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architecture rtl of pll_reset_sync is
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signal locked_sync : std_logic_vector(1 downto 0) := (others => '0');
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signal shreg : std_logic_vector(RESET_CYCLES-1 downto 0) := (others => '0');
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signal cnt : unsigned(5 downto 0) := (others => '0'); -- counts 0..63
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begin
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-- sync
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process(clk)
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| ... | ... | |
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begin
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if rising_edge(clk) then
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if locked_sync(1) = '0' then
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shreg <= (others => '0');
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else
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shreg <= shreg(RESET_CYCLES-2 downto 0) & '1';
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cnt <= (others => '0');
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elsif cnt /= RESET_CYCLES-1 then
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cnt <= cnt + 1;
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end if;
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end if;
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end process;
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reset_n <= shreg(RESET_CYCLES-1);
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reset_n <= '1' when cnt = RESET_CYCLES-1 else '0';
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end architecture;
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Cut a few registers