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Revision 149

Added by markw over 11 years ago

Merged in Dmitriys Aeon lite port. This does not build for me yet - needs a few more adjustments...

View differences:

aeon_lite/Aeon.prj
address_decoder.vhdl
antic_counter.vhdl
antic_dma_clock.vhdl
antic.vhdl
complete_address_decoder.vhdl
cpu_65xx_e.vhd
cpu_65xx_a.vhd
cpu_6510.vhd
cpu.vhd
delay_line.vhdl
enable_divider.vhdl
generic_ram_infer.vhdl
gtia_palette.vhdl
gtia_player.vhdl
gtia_priority.vhdl
gtia.vhdl
irq_glue.vhdl
pia.vhdl
pokey_countdown_timer.vhdl
pokey_keyboard_scanner.vhdl
pokey_mixer.vhdl
pokey_noise_filter.vhdl
pokey.vhdl
pokey_poly_17_9.vhdl
pokey_poly_4.vhdl
pokey_poly_5.vhdl
reg_file.vhdl
shared_enable.vhdl
simple_counter.vhdl
synchronizer.vhdl
syncreset_enable_divider.vhd
wide_delay_line.vhdl
basic.vhdl
os16.vhdl
os2.vhdl
os8.vhdl
os16_loop.vhdl
internalromram.vhd
covox.vhd
ps2_keyboard.vhdl
ps2_to_atari800.vhdl
atari800core.vhd
atari800core_simple_sdram.vhd
dac.vhd
nes_gamepad.vhd
sram_statemachine.vhd
zpu_rom.vhdl
pll.xco
pll.xise
scandouble_ram_infer.vhdl
scandoubler.vhdl
spi_master.vhd
zpupkg.vhd
zpu_config_regs.vhdl
zpu_glue.vhdl
zpu_core.vhd
zpucore.vhd
atari.vhd
aeon_lite/Aeon.scr
run
-ifn Aeon.prj
-ifmt VHDL
-ofn Aeon.ngc
-ofmt NGC
-p XC3S1600E-FG320-4
-opt_mode Area
-opt_level 1
-keep_hierarchy yes
-top ATARI
aeon_lite/Aeon.ucf
# 50NHz Clock
NET "CLK_50" LOC = P123 | IOSTANDARD = LVTTL;
NET "CLK_50" TNM_NET = "CLK_50";
TIMESPEC TS_CLK_50 = PERIOD "CLK_50" 50 MHz HIGH 50 %;
# VGA
NET "VGA_R[3]" LOC = P83 | IOSTANDARD = LVTTL;
NET "VGA_R[2]" LOC = P82 | IOSTANDARD = LVTTL;
NET "VGA_R[1]" LOC = P81 | IOSTANDARD = LVTTL;
NET "VGA_R[0]" LOC = P80 | IOSTANDARD = LVTTL;
NET "VGA_G[3]" LOC = P79 | IOSTANDARD = LVTTL;
NET "VGA_G[2]" LOC = P78 | IOSTANDARD = LVTTL;
NET "VGA_G[1]" LOC = P75 | IOSTANDARD = LVTTL;
NET "VGA_G[0]" LOC = P74 | IOSTANDARD = LVTTL;
NET "VGA_B[3]" LOC = P67 | IOSTANDARD = LVTTL;
NET "VGA_B[2]" LOC = P66 | IOSTANDARD = LVTTL;
NET "VGA_B[1]" LOC = P64 | IOSTANDARD = LVTTL;
NET "VGA_B[0]" LOC = P62 | IOSTANDARD = LVTTL;
NET "VGA_VSYNC" LOC = P61 | IOSTANDARD = LVTTL;
NET "VGA_HSYNC" LOC = P59 | IOSTANDARD = LVTTL;
#NET "BTN_RST" LOC = P114 | IOSTANDARD = LVTTL;
#NET "BTN_NMI" LOC = P115 | IOSTANDARD = LVTTL;
# Sound
NET "SOUND_L" LOC = P84 | IOSTANDARD = LVTTL;
NET "SOUND_R" LOC = P85 | IOSTANDARD = LVTTL;
# SPI Communication
#NET "COMM_CSA" LOC = P69 | IOSTANDARD = LVTTL;
#NET "COMM_CSD" LOC = P60 | IOSTANDARD = LVTTL;
#NET "COMM_MISO" LOC = P50 | IOSTANDARD = LVTTL;
#NET "COMM_MOSI" LOC = P65 | IOSTANDARD = LVTTL;
#NET "COMM_SCK" LOC = P70 | IOSTANDARD = LVTTL | CLOCK_DEDICATED_ROUTE = FALSE;
#NET "COMM_RDY" LOC = P39 | IOSTANDARD = LVTTL;
# SD-Card & SPI-Flash
NET "SD_MOSI" LOC = P41 | IOSTANDARD = LVTTL;
NET "SD_MISO" LOC = P38 | IOSTANDARD = LVTTL;
NET "SD_SCK" LOC = P40 | IOSTANDARD = LVTTL;
NET "SD_CS" LOC = P44 | IOSTANDARD = LVTTL;
#NET "FL_CS" LOC = P43 | IOSTANDARD = LVTTL;
# SRAM
NET "SRAM_A[0]" LOC = P21 | IOSTANDARD = LVTTL;
NET "SRAM_A[1]" LOC = P17 | IOSTANDARD = LVTTL;
NET "SRAM_A[2]" LOC = P16 | IOSTANDARD = LVTTL;
NET "SRAM_A[3]" LOC = P15 | IOSTANDARD = LVTTL;
NET "SRAM_A[4]" LOC = P14 | IOSTANDARD = LVTTL;
NET "SRAM_A[5]" LOC = P144 | IOSTANDARD = LVTTL;
NET "SRAM_A[6]" LOC = P143 | IOSTANDARD = LVTTL;
NET "SRAM_A[7]" LOC = P142 | IOSTANDARD = LVTTL;
NET "SRAM_A[8]" LOC = P141 | IOSTANDARD = LVTTL;
NET "SRAM_A[9]" LOC = P140 | IOSTANDARD = LVTTL;
NET "SRAM_A[10]" LOC = P124 | IOSTANDARD = LVTTL;
NET "SRAM_A[11]" LOC = P126 | IOSTANDARD = LVTTL;
NET "SRAM_A[12]" LOC = P127 | IOSTANDARD = LVTTL;
NET "SRAM_A[13]" LOC = P131 | IOSTANDARD = LVTTL;
NET "SRAM_A[14]" LOC = P132 | IOSTANDARD = LVTTL;
NET "SRAM_A[15]" LOC = P32 | IOSTANDARD = LVTTL;
NET "SRAM_A[16]" LOC = P33 | IOSTANDARD = LVTTL;
NET "SRAM_A[17]" LOC = P34 | IOSTANDARD = LVTTL;
#NET "SRAM_A[18]" LOC = P133 | IOSTANDARD = LVTTL;
NET "SRAM_D[0]" LOC = P11 | IOSTANDARD = LVTTL;
NET "SRAM_D[1]" LOC = P10 | IOSTANDARD = LVTTL;
NET "SRAM_D[2]" LOC = P9 | IOSTANDARD = LVTTL;
NET "SRAM_D[3]" LOC = P8 | IOSTANDARD = LVTTL;
NET "SRAM_D[4]" LOC = P7 | IOSTANDARD = LVTTL;
NET "SRAM_D[5]" LOC = P6 | IOSTANDARD = LVTTL;
NET "SRAM_D[6]" LOC = P5 | IOSTANDARD = LVTTL;
NET "SRAM_D[7]" LOC = P2 | IOSTANDARD = LVTTL;
NET "SRAM_D[8]" LOC = P134 | IOSTANDARD = LVTTL;
NET "SRAM_D[9]" LOC = P137 | IOSTANDARD = LVTTL;
NET "SRAM_D[10]" LOC = P138 | IOSTANDARD = LVTTL;
NET "SRAM_D[11]" LOC = P139 | IOSTANDARD = LVTTL;
NET "SRAM_D[12]" LOC = P22 | IOSTANDARD = LVTTL;
NET "SRAM_D[13]" LOC = P23 | IOSTANDARD = LVTTL;
NET "SRAM_D[14]" LOC = P24 | IOSTANDARD = LVTTL;
NET "SRAM_D[15]" LOC = P26 | IOSTANDARD = LVTTL;
NET "SRAM_CE0" LOC = P12 | IOSTANDARD = LVTTL;
NET "SRAM_CE1" LOC = P35 | IOSTANDARD = LVTTL;
NET "SRAM_LB" LOC = P27 | IOSTANDARD = LVTTL;
NET "SRAM_OE" LOC = P30 | IOSTANDARD = LVTTL;
NET "SRAM_UB" LOC = P29 | IOSTANDARD = LVTTL;
NET "SRAM_WE" LOC = P1 | IOSTANDARD = LVTTL;
# Gamepads
NET "JOY_LOAD" LOC = P118 | IOSTANDARD = LVTTL;
NET "JOY_CLK" LOC = P119 | IOSTANDARD = LVTTL;
NET "JOY_DATA0" LOC = P120 | IOSTANDARD = LVTTL;
NET "JOY_DATA1" LOC = P121 | IOSTANDARD = LVTTL;
# Keyboard & Mouse
NET "KB_CLK" LOC = P58 | IOSTANDARD = LVTTL;
NET "KB_DAT" LOC = P57 | IOSTANDARD = LVTTL;
#NET "MOUSE_CLK" LOC = P55 | IOSTANDARD = LVTTL;
#NET "MOUSE_DATA" LOC = P56 | IOSTANDARD = LVTTL;
##############################################################
#NET "IO[0]" LOC = P117 | IOSTANDARD = LVTTL;
#NET "IO[1]" LOC = P116 | IOSTANDARD = LVTTL;
#NET "IO[2]" LOC = P115 | IOSTANDARD = LVTTL;
#NET "IO[3]" LOC = P114 | IOSTANDARD = LVTTL;
#NET "IO[4]" LOC = P112 | IOSTANDARD = LVTTL;
#NET "IO[5]" LOC = P111 | IOSTANDARD = LVTTL;
#NET "IO[6]" LOC = P105 | IOSTANDARD = LVTTL;
#NET "IO[7]" LOC = P104 | IOSTANDARD = LVTTL;
#NET "IO[8]" LOC = P102 | IOSTANDARD = LVTTL;
#NET "IO[9]" LOC = P101 | IOSTANDARD = LVTTL;
#NET "IO[10]" LOC = P100 | IOSTANDARD = LVTTL;
#NET "IO[11]" LOC = P99 | IOSTANDARD = LVTTL;
#NET "IO[12]" LOC = P98 | IOSTANDARD = LVTTL;
#NET "IO[13]" LOC = P97 | IOSTANDARD = LVTTL;
#NET "IO[14]" LOC = P95 | IOSTANDARD = LVTTL;
#NET "IO[15]" LOC = P94 | IOSTANDARD = LVTTL;
#NET "IO[16]" LOC = P93 | IOSTANDARD = LVTTL;
#NET "IO[17]" LOC = P92 | IOSTANDARD = LVTTL;
#NET "IO[18]" LOC = P88 | IOSTANDARD = LVTTL;
#NET "IO[19]" LOC = P87 | IOSTANDARD = LVTTL;
#NET "COMM[6]" LOC = P45 | IOSTANDARD = LVTTL;
#NET "COMM[7]" LOC = P44 | IOSTANDARD = LVTTL;
#NET "COMM[8]" LOC = P43 | IOSTANDARD = LVTTL;
#NET "COMM[9]" LOC = P41 | IOSTANDARD = LVTTL;
#NET "COMM[10]" LOC = P40 | IOSTANDARD = LVTTL;
aeon_lite/Aeon.ut
-g DonePin:PULLUP
-g TdoPin:PULLNONE
-g M0Pin:PULLUP
-g M1Pin:PULLUP
-g M2Pin:PULLUP
-g StartUpClk:CCLK
-g DriveDone:Yes
-g Binary:Yes
aeon_lite/pll/pll/simulation/functional/simulate_mti.do
# file: simulate_mti.do
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# set up the working directory
set work work
vlib work
# compile all of the files
vcom -work work ../../../pll.vhd
vcom -work work ../../example_design/pll_exdes.vhd
vcom -work work ../pll_tb.vhd
# run the simulation
vsim -t ps -voptargs="+acc" -L unisim work.pll_tb
do wave.do
when {end_of_sim} {echo "End of Simulation"; stop}
log pll_tb/dut/counter
log -r /*
run 50000ns
aeon_lite/pll/pll/simulation/functional/simulate_vcs.sh
#!/bin/sh
# file: simulate_vcs.sh
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# remove old files
rm -rf simv* csrc DVEfiles AN.DB
# compile all of the files
# Note that -sverilog is not strictly required- You can
# remove the -sverilog if you change the type of the
# localparam for the periods in the testbench file to
# [63:0] from time
vhdlan -xlrm ../../../pll.vhd \
../../example_design/pll_exdes.vhd \
../pll_tb.vhd
# prepare the simulation
vcs +vcs+lic+wait -xlrm -debug pll_tb
# run the simulation
./simv -xlrm -ucli -i ucli_commands.key
# launch the viewer
#dve -vpd vcdplus.vpd -session vcs_session.tcl
aeon_lite/pll/pll/simulation/pll_tb.vhd
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 20.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
LOCKED => LOCKED);
-- Freq Check
end test;
aeon_lite/pll/pll/implement/planAhead_rdn.bat
REM file: planAhead_rdn.sh
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
REM-----------------------------------------------------------------------------
REM Script to synthesize and implement the RTL provided for the XADC wizard
REM-----------------------------------------------------------------------------
del \f results
mkdir results
cd results
planAhead -mode batch -source ..\planAhead_rdn.tcl
aeon_lite/pll/pll/implement/planAhead_rdn.tcl
# file : planAhead_rdn.tcl
#
# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
set device xc6slx9tqg144-3
set projName pll
set design pll
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module pll_exdes
set_property top pll_exdes [get_property srcset [current_run]]
add_files -norecurse {../../../pll.vhd}
add_files -norecurse {../../example_design/pll_exdes.vhd}
import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_exdes.xdc}
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module pll_exdes -file routed.sdf
write_vhdl -file routed.vhd
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
aeon_lite/pll/pll/implement/xst.scr
run
-ifmt MIXED
-top pll_exdes
-p xc6slx9-tqg144-3
-ifn xst.prj
-ofn pll_exdes
-keep_hierarchy soft
-equivalent_register_removal no
-max_fanout 65535
aeon_lite/pll/pll/simulation/functional/simulate_isim.bat
REM file: simulate_isim.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
vhpcomp -work work ..\..\..\pll.vhd
vhpcomp -work work ..\..\example_design\pll_exdes.vhd
vhpcomp -work work ..\pll_tb.vhd
REM compile the project
fuse work.pll_tb -L unisim -o pll_isim.exe
REM run the simulation script
.\pll_isim.exe -gui -tclbatch simcmds.tcl
aeon_lite/atari.vhd
---------------------------------------------------------------------------
-- Atari800-Core wrapper
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- ilovespeccy@speccyland.net
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
-- New Files:
-- DAC.VHD - Delta-Sigma-DAC from Xilinx Appnotes
-- NES-GAMEPAD.VHD - NES-Gamepad controller
-- SRAM-STATEMACHINE.VHD - SRAM (2 x 256KB x 16bit) Controller
-- Changed Files:
-- PS2_TO_ATARI800.VHD - Added PS2_KEYS Output
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ATARI is
port (
CLK_50 : in std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
KB_CLK : in std_logic;
KB_DAT : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end ATARI;
architecture rtl of ATARI is
signal CLK : std_logic;
signal LOCKED : std_logic;
signal RESET_N : std_logic;
-- Pokey Keyboard
signal KEYBOARD_SCAN : std_logic_vector(5 downto 0);
signal KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
-- GTIA Consol Keys
signal CONSOL_START : std_logic;
signal CONSOL_SELECT : std_logic;
signal CONSOL_OPTION : std_logic;
signal FKEYS : std_logic_vector(11 downto 0);
signal PS2_KEYS : std_logic_vector(511 downto 0);
-- Gamepads
signal GAMEPAD0 : std_logic_vector(7 downto 0);
signal GAMEPAD1 : std_logic_vector(7 downto 0);
signal JOY1_n : std_logic_vector(4 downto 0);
signal JOY2_n : std_logic_vector(4 downto 0);
-- Video
signal VIDEO_R : std_logic_vector(7 downto 0);
signal VIDEO_G : std_logic_vector(7 downto 0);
signal VIDEO_B : std_logic_vector(7 downto 0);
signal VIDEO_VS : std_logic;
signal VIDEO_HS : std_logic;
signal PAL : std_logic := '0';
signal VGA : std_logic := '1';
signal SCANLINES : std_logic := '0';
-- Scandoubler
signal SCANDOUBLE_CLK : std_logic;
signal HALF_SCANDOUBLE_ENABLE_REG : std_logic;
signal HALF_SCANDOUBLE_ENABLE_NEXT : std_logic;
-- Audio
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
-- SDRAM (SRAM)
signal SDRAM_REQUEST : std_logic;
signal SDRAM_REQUEST_COMPLETE : std_logic;
signal SDRAM_WRITE_ENABLE : std_logic;
signal SDRAM_ADDR : std_logic_vector(22 DOWNTO 0);
signal SDRAM_DO : std_logic_vector(31 DOWNTO 0);
signal SDRAM_DI : std_logic_vector(31 DOWNTO 0);
signal SDRAM_WIDTH_8BIT_ACCESS : std_logic;
signal SDRAM_WIDTH_16BIT_ACCESS : std_logic;
signal SDRAM_WIDTH_32BIT_ACCESS : std_logic;
-- DMA/Virtual Drive
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
signal DMA_FETCH : std_logic;
signal DMA_32BIT_WRITE_ENABLE : std_logic;
signal DMA_16BIT_WRITE_ENABLE : std_logic;
signal DMA_8BIT_WRITE_ENABLE : std_logic;
signal DMA_READ_ENABLE : std_logic;
signal DMA_MEMORY_READY : std_logic;
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
-- System Control from ZPU
signal ZPU_POKEY_ENABLE : std_logic;
signal ZPU_SIO_TXD : std_logic;
signal ZPU_SIO_RXD : std_logic;
signal ZPU_SIO_COMMAND : std_logic;
alias PAUSE_ATARI : std_logic is ZPU_OUT1(0);
alias RESET_ATARI : std_logic is ZPU_OUT1(1);
alias SPEED_6502 : std_logic_vector(5 downto 0) is ZPU_OUT1(7 downto 2);
alias RAM_SELECT : std_logic_vector(2 downto 0) is ZPU_OUT1(10 downto 8);
alias ROM_SELECT : std_logic_vector(5 downto 0) is ZPU_OUT1(16 downto 11);
signal reset_n_inc_zpu : std_logic;
signal zpu_in1 : std_logic_vector(31 downto 0);
begin
u_PLL : entity work.PLL
port map (
CLKIN => CLK_50,
CLKOUT => CLK,
CLKOUT2 => SCANDOUBLE_CLK,
LOCKED => LOCKED );
u_DAC_L : entity work.dac
port map (
CLK_I => CLK,
RES_N_I => RESET_N,
DAC_I => AUDIO_L_PCM,
DAC_O => SOUND_L );
u_DAC_R : entity work.dac
port map (
CLK_I => CLK,
RES_N_I => RESET_N,
DAC_I => AUDIO_R_PCM,
DAC_O => SOUND_R );
u_KEYBOARD : entity work.ps2_to_atari800
port map(
CLK => CLK,
RESET_N => RESET_N,
PS2_CLK => KB_CLK,
PS2_DAT => KB_DAT,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
FKEYS => FKEYS,
PS2_KEYS => PS2_KEYS );
u_JOYSTICKS : entity work.nes_gamepad
port map(
CLK => CLK,
RESET => not RESET_N,
JOY_CLK => JOY_CLK,
JOY_LOAD => JOY_LOAD,
JOY_DATA0 => JOY_DATA0,
JOY_DATA1 => JOY_DATA1,
JOY0_BUTTONS => GAMEPAD0,
JOY1_BUTTONS => GAMEPAD1,
JOY0_CONNECTED => OPEN,
JOY1_CONNECTED => OPEN );
reset_n_inc_zpu <= RESET_N and not (RESET_ATARI);
u_ATARI800_CORE : entity work.atari800core_simple_sdram
generic map(
CYCLE_LENGTH => 16,
INTERNAL_ROM => 0,
INTERNAL_RAM => 0,
PALETTE => 0,
VIDEO_BITS => 8,
LOW_MEMORY => 1 )
port map(
CLK => CLK,
RESET_N => reset_n_inc_zpu,
VIDEO_VS => VIDEO_VS,
VIDEO_HS => VIDEO_HS,
VIDEO_B => VIDEO_B,
VIDEO_G => VIDEO_G,
VIDEO_R => VIDEO_R,
VIDEO_BLANK => OPEN,
VIDEO_BURST => OPEN,
VIDEO_START_OF_FIELD => OPEN,
VIDEO_ODD_LINE => OPEN,
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
JOY1_n => JOY1_n,
JOY2_n => JOY2_n,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
SIO_COMMAND => ZPU_SIO_COMMAND,
SIO_RXD => ZPU_SIO_TXD,
SIO_TXD => ZPU_SIO_RXD,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => OPEN,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => SDRAM_DO,
SDRAM_DI => SDRAM_DI,
SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32BIT_ACCESS,
SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16BIT_ACCESS,
SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8BIT_ACCESS,
SDRAM_REFRESH => OPEN,
DMA_FETCH => DMA_FETCH,
DMA_READ_ENABLE => DMA_READ_ENABLE,
DMA_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
DMA_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
DMA_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
DMA_ADDR => DMA_ADDR_FETCH,
DMA_WRITE_DATA => DMA_WRITE_DATA,
MEMORY_READY_DMA => DMA_MEMORY_READY,
DMA_MEMORY_DATA => DMA_MEMORY_DATA,
RAM_SELECT => RAM_SELECT,
ROM_SELECT => ROM_SELECT,
PAL => PAL,
HALT => PAUSE_ATARI,
THROTTLE_COUNT_6502 => SPEED_6502 );
u_SRAM : entity work.sram_statemachine
port map (
CLK => CLK,
RESET_N => reset_n_inc_zpu,
ADDRESS_IN => SDRAM_ADDR,
DATA_IN => SDRAM_DI,
DATA_OUT => SDRAM_DO,
WRITE_EN => SDRAM_WRITE_ENABLE,
REQUEST => SDRAM_REQUEST,
BYTE_ACCESS => SDRAM_WIDTH_8BIT_ACCESS,
WORD_ACCESS => SDRAM_WIDTH_16BIT_ACCESS,
LONGWORD_ACCESS => SDRAM_WIDTH_32BIT_ACCESS,
COMPLETE => SDRAM_REQUEST_COMPLETE,
SRAM_ADDR => SRAM_A,
SRAM_DQ => SRAM_D,
SRAM_CE0_N => SRAM_CE0,
SRAM_CE1_N => SRAM_CE1,
SRAM_OE_N => SRAM_OE,
SRAM_WE_N => SRAM_WE,
SRAM_UB_N => SRAM_UB,
SRAM_LB_N => SRAM_LB );
u_ZPU : entity work.zpucore
generic map (
PLATFORM => 1,
SPI_CLOCK_DIV => 1 )
port map (
CLK => CLK,
RESET_N => RESET_N,
ZPU_ADDR_FETCH => DMA_ADDR_FETCH,
ZPU_DATA_OUT => DMA_WRITE_DATA,
ZPU_FETCH => DMA_FETCH,
ZPU_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
ZPU_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
ZPU_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
ZPU_READ_ENABLE => DMA_READ_ENABLE,
ZPU_MEMORY_READY => DMA_MEMORY_READY,
ZPU_MEMORY_DATA => DMA_MEMORY_DATA,
ZPU_ADDR_ROM => ZPU_ADDR_ROM,
ZPU_ROM_DATA => ZPU_ROM_DATA,
ZPU_SD_DAT0 => SD_MISO,
ZPU_SD_CLK => SD_SCK,
ZPU_SD_CMD => SD_MOSI,
ZPU_SD_DAT3 => SD_CS,
ZPU_POKEY_ENABLE => ZPU_POKEY_ENABLE,
ZPU_SIO_TXD => ZPU_SIO_TXD,
ZPU_SIO_RXD => ZPU_SIO_RXD,
ZPU_SIO_COMMAND => ZPU_SIO_COMMAND,
ZPU_IN1 => zpu_in1,
ZPU_IN2 => X"00000000",
ZPU_IN3 => X"00000000",
ZPU_IN4 => X"00000000",
ZPU_OUT1 => ZPU_OUT1,
ZPU_OUT2 => OPEN,
ZPU_OUT3 => OPEN,
ZPU_OUT4 => OPEN );
zpu_in1 <= X"00000" & FKEYS;
u_ZPUROM : entity work.zpu_rom
port map (
CLOCK => CLK,
ADDRESS => ZPU_ADDR_ROM(13 downto 2),
Q => ZPU_ROM_DATA );
u_ZPUPOKEY : entity work.enable_divider
generic map (
COUNT => 16 )
port map (
CLK => CLK,
RESET_N => RESET_N,
ENABLE_IN => '1',
ENABLE_OUT => ZPU_POKEY_ENABLE);
-- Scandoubler
process(SCANDOUBLE_CLK, RESET_N, RESET_ATARI)
begin
if ((RESET_N and not (RESET_ATARI)) = '0') then
HALF_SCANDOUBLE_ENABLE_REG <= '0';
elsif (SCANDOUBLE_CLK'event and SCANDOUBLE_CLK = '1') then
HALF_SCANDOUBLE_ENABLE_REG <= HALF_SCANDOUBLE_ENABLE_NEXT;
end if;
end process;
HALF_SCANDOUBLE_ENABLE_NEXT <= not(HALF_SCANDOUBLE_ENABLE_REG);
u_SCANDOUBLER : entity work.scandoubler
port map (
CLK => SCANDOUBLE_CLK,
RESET_N => reset_n_inc_zpu,
VGA => VGA,
COMPOSITE_ON_HSYNC => not VGA,
COLOUR_ENABLE => HALF_SCANDOUBLE_ENABLE_REG,
DOUBLED_ENABLE => VGA,
SCANLINES_ON => SCANLINES,
COLOUR_IN => VIDEO_B,
VSYNC_IN => VIDEO_VS,
HSYNC_IN => VIDEO_HS,
R => VGA_R,
G => VGA_G,
B => VGA_B,
VSYNC => VGA_VSYNC,
HSYNC => VGA_HSYNC );
RESET_N <= LOCKED;
-- NES Gamepad 1 & Cursor keys on keyboard
JOY1_n <= (not GAMEPAD0(7) and not GAMEPAD0(6) and not PS2_KEYS(16#014#)) &
(not GAMEPAD0(0) and not PS2_KEYS(16#174#)) &
(not GAMEPAD0(1) and not PS2_KEYS(16#16B#)) &
(not GAMEPAD0(2) and not PS2_KEYS(16#172#)) &
(not GAMEPAD0(3) and not PS2_KEYS(16#175#)) ;
-- NES Gamepad 2
JOY2_n <= (not GAMEPAD1(7) and not GAMEPAD1(6)) & not GAMEPAD1(0) & not GAMEPAD1(1) & not GAMEPAD1(2) & not GAMEPAD1(3);
-- Switch video mode
-- VGA/TV (Ins)
process(PS2_KEYS)
begin
if rising_edge(PS2_KEYS(16#170#)) then
VGA <= not VGA;
end if;
end process;
-- PAL/NTSC (Home)
process(PS2_KEYS)
begin
if rising_edge(PS2_KEYS(16#16C#)) then
PAL <= not PAL;
end if;
end process;
-- Scanlines on/off (Page Up)
process(PS2_KEYS)
begin
if rising_edge(PS2_KEYS(16#17D#)) then
SCANLINES <= not SCANLINES;
end if;
end process;
end rtl;
aeon_lite/build.sh
#!/bin/bash
name=Aeon
args=$@
shift
. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
mkdir -p build
pushd build
# copy source files
cp -p ../*.vhd .
cp -p ../*.vhdl .
cp -p ../pll/* .
cp -p ../../common/a8core/*.vhd .
cp -p ../../common/a8core/*.vhdl .
cp -p ../../common/components/*.vhd .
cp -p ../../common/components/*.vhdl .
cp -p ../../common/zpu/*.vhd .
cp -p ../../common/zpu/*.vhdl .
cp -p ../$name.ucf .
cp -p ../$name.ut .
cp -p ../$name.scr .
cp -p ../$name.prj .
if [ "${args[0]}" != "-xil" ]; then
echo "Starting Synthesis..."
xst -ifn $name.scr -ofn $name.srp || exit 1
fi
echo "Starting Translate..."
ngdbuild -nt on -uc $name.ucf $name.ngc $name.ngd || exit 1
echo "Starting Map..."
map -pr b $name.ngd -o $name.ncd $name.pcf || exit 1
echo "Starting Place & Route..."
par -w -ol std $name.ncd $name.ncd $name.pcf || exit 1
echo "Starting Timing Analysis..."
trce -v 10 -o $name.twr $name.ncd $name.pcf || exit 1
echo "Starting Bitgen..."
bitgen $name.ncd $name.bit -w -f $name.ut || exit 1
popd
cp build/$name.bin core/atari800.bin
aeon_lite/dac.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 15
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;
aeon_lite/pll/pll/simulation/functional/simulate_mti.bat
REM file: simulate_mti.bat
REM
REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
REM
REM set up the working directory
vlib work
REM compile all of the files
vcom -work work ..\..\..\pll.vhd
vcom -work work ..\..\example_design\pll_exdes.vhd
vcom -work work ..\pll_tb.vhd
REM run the simulation
vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_tb
aeon_lite/nes_gamepad.vhd
---------------------------------------------------------------------------
-- NES-Controller Module
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- ilovespeccy@speccyland.net
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
------------------
-- Bit - Button --
-- (1 = pressed)
------------------
-- 7 A
-- 6 B
-- 5 Select
-- 4 Start
-- 3 Up
-- 2 Down
-- 1 Left
-- 0 Right
------------------
entity nes_gamepad is
generic (
CLK_FREQ : integer := 25000000;
TICK_FREQ : integer := 20000 );
port (
CLK : in std_logic;
RESET : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
JOY0_BUTTONS : out std_logic_vector(7 downto 0);
JOY1_BUTTONS : out std_logic_vector(7 downto 0);
JOY0_CONNECTED : out std_logic; -- 1 when gamepad connected
JOY1_CONNECTED : out std_logic );
end nes_gamepad;
architecture RTL of nes_gamepad is
signal TICK : integer range 0 to (CLK_FREQ / TICK_FREQ);
signal STATE : integer range 0 to 17;
signal DATA0 : std_logic_vector(7 downto 0);
signal DATA1 : std_logic_vector(7 downto 0);
begin
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= 0;
JOY_CLK <= '0';
JOY_LOAD <= '0';
TICK <= 0;
JOY0_BUTTONS <= "00000000";
JOY0_BUTTONS <= "00000000";
JOY0_CONNECTED <= '0';
JOY1_CONNECTED <= '0';
else
TICK <= TICK + 1;
if TICK = (CLK_FREQ / TICK_FREQ) then
TICK <= 0;
STATE <= STATE + 1;
case STATE is
when 0 =>
JOY_LOAD <= '1';
when 1 =>
JOY_LOAD <= '0';
DATA0(7) <= JOY_DATA0;
DATA1(7) <= JOY_DATA1;
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 =>
JOY_CLK <= '1';
when 3 =>
JOY_CLK <= '0';
DATA0(6) <= JOY_DATA0;
DATA1(6) <= JOY_DATA1;
when 5 =>
JOY_CLK <= '0';
DATA0(5) <= JOY_DATA0;
DATA1(5) <= JOY_DATA1;
when 7 =>
JOY_CLK <= '0';
DATA0(4) <= JOY_DATA0;
DATA1(4) <= JOY_DATA1;
when 9 =>
JOY_CLK <= '0';
DATA0(3) <= JOY_DATA0;
DATA1(3) <= JOY_DATA1;
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