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diff -ur atari800core_v1_20140121_mcc216/address_decoder.vhdl atari800core_v1_20140312_mist/address_decoder.vhdl
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--- atari800core_v1_20140121_mcc216/address_decoder.vhdl 2014-01-30 21:32:16.000000000 +0000
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+++ atari800core_v1_20140312_mist/address_decoder.vhdl 2014-03-09 20:12:21.000000000 +0000
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@@ -59,9 +59,11 @@
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reset_n : in std_logic;
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- rom_select : in std_logic_vector(1 downto 0);
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+ rom_select : in std_logic_vector(5 downto 0);
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+ cart_select : in std_logic_vector(6 downto 0);
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+ cart_activate : in std_logic;
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- ram_select : in std_logic_vector(1 downto 0);
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+ ram_select : in std_logic_vector(2 downto 0);
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CART_RD4 : in std_logic;
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CART_RD5 : in std_logic;
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@@ -88,7 +90,8 @@
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PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
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RAM_WR_ENABLE : OUT STD_LOGIC;
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PBI_WR_ENABLE : OUT STD_LOGIC;
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-
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+ D6_WR_ENABLE : OUT STD_LOGIC;
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+
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-- ROM and RAM have extended address busses to allow for bank switching etc.
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ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
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RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
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@@ -147,12 +150,16 @@
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signal notify_cpu : std_logic;
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signal start_request : std_logic;
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+ signal extended_access_addr : std_logic;
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signal extended_access_cpu_or_antic : std_logic;
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signal extended_access_antic : std_logic;
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signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
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signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
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+ signal extended_self_test : std_logic;
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+ signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
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+
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-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
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signal state_next : std_logic_vector(1 downto 0);
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signal state_reg : std_logic_vector(1 downto 0);
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@@ -173,6 +180,19 @@
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signal fetch_wait_next : std_logic_vector(8 downto 0);
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signal fetch_wait_reg : std_logic_vector(8 downto 0);
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+ signal rom_in_ram : std_logic;
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+
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+ signal antic_fetch_real_next : std_logic;
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+ signal antic_fetch_real_reg : std_logic;
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+ signal cpu_fetch_real_next : std_logic;
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+ signal cpu_fetch_real_reg : std_logic;
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+
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+ signal SDRAM_CART_ADDR : std_logic_vector(22 downto 0);
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+ signal SDRAM_BASIC_ROM_ADDR : std_logic_vector(22 downto 0);
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+ signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
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+
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+ signal sdram_only_bank : std_logic;
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+
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BEGIN
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-- register
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process(clk,reset_n)
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@@ -187,7 +207,10 @@
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data_write_reg <= (others=> '0');
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--sdram_request_reg <= '0';
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fetch_wait_reg <= (others=>'0');
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- elsif (clk'event and clk='1') then
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+
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+ cpu_fetch_real_reg <= '0';
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+ antic_fetch_real_reg <= '0';
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+ elsif (clk'event and clk='1') then
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addr_reg <= addr_next;
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state_reg <= state_next;
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width_8bit_reg <= width_8bit_next;
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@@ -197,6 +220,9 @@
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data_write_reg <= data_WRITE_next;
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--sdram_request_reg <= sdram_request_next;
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fetch_wait_reg <= fetch_wait_next;
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+
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+ cpu_fetch_real_reg <= cpu_fetch_real_next;
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+ antic_fetch_real_reg <= antic_fetch_real_next;
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end if;
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end process;
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@@ -219,7 +245,7 @@
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-- state machine impl
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fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
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- process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
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+ process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
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begin
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start_request <= '0';
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notify_antic <= '0';
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@@ -235,6 +261,9 @@
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width_32bit_next <= width_32bit_reg;
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write_enable_next <= write_enable_reg;
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+ antic_fetch_real_next <= antic_fetch_real_reg;
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+ cpu_fetch_real_next <= cpu_fetch_real_reg;
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+
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case state_reg is
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when state_idle =>
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fetch_wait_next <= (others=>'0');
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@@ -255,6 +284,7 @@
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else
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state_next <= state_waiting_antic;
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end if;
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+ antic_fetch_real_next <= '1';
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when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
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start_request <= '1';
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addr_next <= zpu_ADDR;
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@@ -282,6 +312,7 @@
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else
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state_next <= state_waiting_cpu;
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end if;
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+ cpu_fetch_real_next <= '1';
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when "000" =>
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-- no requests
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end case;
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@@ -312,7 +343,7 @@
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SDRAM_REQUEST <= sdram_chip_select;
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--SDRAM_REQUEST <= sdram_request_next;
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- SDRAM_REFRESH <= fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
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+ SDRAM_REFRESH <= '0'; --fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
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SDRAM_READ_EN <= not(write_enable_next);
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SDRAM_WRITE_EN <= write_enable_next;
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@@ -327,11 +358,78 @@
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--sdram_request_next <= sdram_request_reg xor sdram_chip_select;
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-- Calculate which memory area to use
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+ extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
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extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
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- extended_access_antic <= (antic_fetch and not(portb(5)));
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- extended_access_cpu <= not(antic_fetch) and not(portb(4));
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+ extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
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+ extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
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+ extended_access_either <= extended_access_addr and not(portb(4));
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+ sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
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+
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+ process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
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+ begin
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+ extended_bank <= "0000000"&addr_next(15 downto 14);
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+ extended_self_test <= '1';
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+
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+ case ram_select is
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+ when "000" => -- 64k
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+ -- default
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+ when "001" => -- 128k
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+ if (extended_access_cpu_or_antic='1') then
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+ extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
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+ end if;
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+ when "010" => -- 320k compy shop
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+ if (extended_access_cpu_or_antic='1') then
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+ extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
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+ extended_self_test <= '0';
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+ end if;
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+ when "011" => -- 320k rambo
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+ if (extended_access_either='1')then
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+ extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
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+ end if;
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+ when "100" => -- 576k compy shop
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+ if (extended_access_cpu_or_antic='1') then
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+ extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
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+ extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
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+ extended_self_test <= '0';
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+ end if;
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+ when "101" => -- 576k rambo
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+ if (extended_access_either='1') then
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+ extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
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+ extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
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+ end if;
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+ when "110" => -- 1088k rambo
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+ if (extended_access_either='1') then
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+ extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
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+ extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
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+ extended_self_test <= '0';
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+ end if;
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+ when "111" => -- 4MB!
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+ if (extended_access_addr='1') then
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+ extended_bank(7 downto 0) <= portb(7 downto 0);
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+ extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
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+ extended_self_test <= and_reduce(portb(6 downto 4)); -- which means self-test is in the middle of half the banks - euuugh, oh well!
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+ end if;
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+ when others =>
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+ -- TODO - portc!
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+ end case;
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+ end process;
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+
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- extended_access_either <= not(portb(4));
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+ -- SRAM memory map (512k)
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+ -- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
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+ -- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
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+ -- SDRAM memory map (8MB)
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+ -- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
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+ -- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
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+ -- to 4MB RAM - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
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+ -- +64k - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
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+ -- SCRATCH - 4MB+64k-5MB
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+ -- CARTS - "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
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+ SDRAM_CART_ADDR <= "101"&cart_select& "0000000000000";
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+ -- BASIC/OS ROM - "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K
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+ SDRAM_BASIC_ROM_ADDR <= "111"&"000000" &"00000000000000";
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+ SDRAM_OS_ROM_ADDR <= "111"&rom_select &"00000000000000";
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+ -- SYSTEM - "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
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process(
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-- address and writing absolutely points us at a device
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@@ -341,7 +439,7 @@
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portb,
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antic_fetch,
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rom_select,
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- extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
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+ ram_select,cart_rd4,cart_rd5,
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use_sdram,
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-- input data from n sources
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@@ -353,7 +451,14 @@
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ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
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-- on new access this is set - we must select the appropriate device - for this cycle only
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- start_request
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+ start_request,
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+
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+ rom_in_ram,
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+
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+ -- SDRAM base addresses
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+ extended_self_test,extended_bank,sdram_only_bank,
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+ SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
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+
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)
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begin
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MEMORY_DATA <= (others => '1');
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@@ -373,6 +478,7 @@
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PIA_WR_ENABLE <= '0';
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PIA_RD_ENABLE <= '0';
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PBI_WR_ENABLE <= '0';
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+ D6_WR_ENABLE <= '0';
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RAM_WR_ENABLE <= write_enable_next;
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SDRAM_WRITE_EN <= write_enable_next;
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@@ -386,13 +492,27 @@
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ram_chip_select <= '0';
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sdram_chip_select <= '0';
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+
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+ rom_in_ram <= '1';
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-- if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
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if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
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- RAM_ADDR(18 downto 16) <= "000";
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- SDRAM_ADDR(22 downto 16) <= "0000000";
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-
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+ SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
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+ SDRAM_ADDR(22 downto 14) <= extended_bank;
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+ RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
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+ RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
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+
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+ if ((use_sdram or sdram_only_bank)='1') then
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+ MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
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+ sdram_chip_select <= start_request;
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+ request_complete <= sdram_request_COMPLETE;
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+ else
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+ MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
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+ ram_chip_select <= start_request;
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+ request_complete <= ram_request_COMPLETE;
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+ end if;
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+
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case addr_next(15 downto 8) is
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-- GTIA
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when X"D0" =>
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@@ -400,6 +520,8 @@
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MEMORY_DATA(7 downto 0) <= GTIA_DATA;
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MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
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request_complete <= '1';
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+ sdram_chip_select <= '0';
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+ ram_chip_select <= '0';
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-- POKEY
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when X"D2" =>
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@@ -413,6 +535,8 @@
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MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
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end if;
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request_complete <= '1';
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+ sdram_chip_select <= '0';
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+ ram_chip_select <= '0';
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-- PIA
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when X"D3" =>
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@@ -420,6 +544,8 @@
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PIA_RD_ENABLE <= '1';
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MEMORY_DATA(7 downto 0) <= PIA_DATA;
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request_complete <= '1';
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+ sdram_chip_select <= '0';
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+ ram_chip_select <= '0';
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-- ANTIC
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when X"D4" =>
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@@ -427,9 +553,13 @@
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MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
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MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
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request_complete <= '1';
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+ sdram_chip_select <= '0';
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+ ram_chip_select <= '0';
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-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
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when X"D5" =>
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+ sdram_chip_select <= '0';
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+ ram_chip_select <= '0';
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if ((CART_RD4 or CART_RD5) = '1') then
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PBI_WR_ENABLE <= write_enable_next;
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MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
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@@ -441,92 +571,39 @@
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request_complete <= '1';
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end if;
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- -- XE RAM
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- when
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- X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
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- |X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
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- |X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
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- |X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
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-
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- if (use_sdram = '1') then
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- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
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- sdram_chip_select <= start_request;
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- request_complete <= sdram_request_COMPLETE;
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- else
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- MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
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- ram_chip_select <= start_request;
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- request_complete <= ram_request_COMPLETE;
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- end if;
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-
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- case ram_select is
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- when "00" => -- 64k
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- -- default
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- when "01" => -- 128k
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- RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
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- SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
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- when "10" => -- 320k compy shop
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- RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
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- SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
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- when "11" => -- 320k rambo
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- RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);
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- SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);
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- end case;
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-
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+ when X"D6" =>
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+ D6_WR_ENABLE <= write_enable_next;
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+ -- TODO - should this still have RAM with covox here?
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+
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-- SELF TEST ROM 0x5000->0x57ff and XE RAM
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when
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X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
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- if (portb(7) = '0' and portb(0) = '1') then
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- --request_complete <= ROM_REQUEST_COMPLETE;
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- --MEMORY_DATA(7 downto 0) <= ROM_DATA;
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- --rom_request <= start_request;
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- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
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+ if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
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+ sdram_chip_select <= '0';
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+ ram_chip_select <= '0';
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+
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+ if (rom_in_ram = '1') then
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+ MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
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+ else
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+ MEMORY_DATA(7 downto 0) <= ROM_DATA;
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+ end if;
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if (write_enable_next = '1') then
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request_complete <= '1';
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else
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- request_complete <= sdram_request_COMPLETE;
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- sdram_chip_select <= start_request;
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+ if (rom_in_ram = '1') then
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+ request_complete <= sdram_request_COMPLETE;
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+ sdram_chip_select <= start_request;
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+ else
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+ request_complete <= rom_request_COMPLETE;
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+ rom_request <= start_request;
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+ end if;
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|
end if;
|
|
--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
|
|
- case rom_select is
|
|
- when "00" =>
|
|
- ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
|
|
- SDRAM_ADDR <="0010000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
|
|
- when "01" =>
|
|
- ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
|
|
- SDRAM_ADDR <="0010000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
|
|
- when "10" =>
|
|
- ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
|
|
- SDRAM_ADDR <="0010000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
|
|
- when "11" =>
|
|
- ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
|
|
- SDRAM_ADDR <= "0010001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
|
|
- end case;
|
|
- else
|
|
- if (use_sdram = '1') then
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
- sdram_chip_select <= start_request;
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- else
|
|
- MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
|
|
- ram_chip_select <= start_request;
|
|
- request_complete <= ram_request_COMPLETE;
|
|
- end if;
|
|
-
|
|
- case ram_select is
|
|
- when "00" => -- 64k
|
|
- -- default
|
|
- when "01" => -- 128k
|
|
- RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
|
|
- SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
|
|
- when "10" => -- 320k compy shop
|
|
- RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
|
|
- SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
|
|
- when "11" => -- 320k rambo
|
|
- RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);
|
|
- SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);
|
|
- end case;
|
|
+ SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
|
|
+ SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
|
|
+ ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
|
|
end if;
|
|
|
|
-- 0x80 cart
|
|
@@ -539,16 +616,8 @@
|
|
rom_request <= start_request;
|
|
CART_S4_n <= '0';
|
|
request_complete <= CART_REQUEST_COMPLETE;
|
|
- else
|
|
- if (use_sdram = '1') then
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
- sdram_chip_select <= start_request;
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- else
|
|
- MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
|
|
- ram_chip_select <= start_request;
|
|
- request_complete <= ram_request_COMPLETE;
|
|
- end if;
|
|
+ sdram_chip_select <= '0';
|
|
+ ram_chip_select <= '0';
|
|
end if;
|
|
|
|
-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
|
|
@@ -561,31 +630,35 @@
|
|
cart_request <= start_request;
|
|
CART_S5_n <= '0';
|
|
request_complete <= CART_REQUEST_COMPLETE;
|
|
+ sdram_chip_select <= '0';
|
|
+ ram_chip_select <= '0';
|
|
else
|
|
if (portb(1) = '0') then
|
|
+ sdram_chip_select <= '0';
|
|
+ ram_chip_select <= '0';
|
|
--request_complete <= ROM_REQUEST_COMPLETE;
|
|
--MEMORY_DATA(7 downto 0) <= ROM_DATA;
|
|
--rom_request <= start_request;
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
+ if (rom_in_ram = '1') then
|
|
+ MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
+ else
|
|
+ MEMORY_DATA(7 downto 0) <= ROM_DATA;
|
|
+ end if;
|
|
if (write_enable_next = '1') then
|
|
request_complete <= '1';
|
|
else
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- sdram_chip_select <= start_request;
|
|
+ if (rom_in_ram = '1') then
|
|
+ request_complete <= sdram_request_COMPLETE;
|
|
+ sdram_chip_select <= start_request;
|
|
+ else
|
|
+ request_complete <= rom_request_COMPLETE;
|
|
+ rom_request <= start_request;
|
|
+ end if;
|
|
end if;
|
|
|
|
ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
|
|
- SDRAM_ADDR <="0010000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
|
|
- else
|
|
- if (use_sdram = '1') then
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
- sdram_chip_select <= start_request;
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- else
|
|
- MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
|
|
- ram_chip_select <= start_request;
|
|
- request_complete <= ram_request_COMPLETE;
|
|
- end if;
|
|
+ SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
|
|
+ SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k
|
|
end if;
|
|
end if;
|
|
|
|
@@ -598,56 +671,38 @@
|
|
|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
|
|
|
|
if (portb(0) = '1') then
|
|
+ sdram_chip_select <= '0';
|
|
+ ram_chip_select <= '0';
|
|
--request_complete <= ROM_REQUEST_COMPLETE;
|
|
--MEMORY_DATA(7 downto 0) <= ROM_DATA;
|
|
--rom_request <= start_request;
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
+ if (rom_in_ram = '1') then
|
|
+ MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
+ else
|
|
+ MEMORY_DATA(7 downto 0) <= ROM_DATA;
|
|
+ end if;
|
|
if (write_enable_next = '1') then
|
|
request_complete <= '1';
|
|
else
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- sdram_chip_select <= start_request;
|
|
+ if (rom_in_ram = '1') then
|
|
+ request_complete <= sdram_request_COMPLETE;
|
|
+ sdram_chip_select <= start_request;
|
|
+ else
|
|
+ request_complete <= rom_request_COMPLETE;
|
|
+ rom_request <= start_request;
|
|
+ end if;
|
|
end if;
|
|
|
|
- case rom_select is
|
|
- when "00" =>
|
|
- ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
|
|
- SDRAM_ADDR <= "0010000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
|
|
- when "01" =>
|
|
- ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
|
|
- SDRAM_ADDR <= "0010000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
|
|
- when "10" =>
|
|
- ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
|
|
- SDRAM_ADDR <= "0010000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
|
|
- when "11" =>
|
|
- ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
|
|
- SDRAM_ADDR <= "0010001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
|
|
- end case;
|
|
-
|
|
- else
|
|
- if (use_sdram = '1') then
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
- sdram_chip_select <= start_request;
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- else
|
|
- MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
|
|
- ram_chip_select <= start_request;
|
|
- request_complete <= ram_request_COMPLETE;
|
|
- end if;
|
|
+ ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
|
|
+ SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
|
|
+ SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
|
|
end if;
|
|
|
|
when others =>
|
|
- if (use_sdram = '1') then
|
|
- MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
|
|
- sdram_chip_select <= start_request;
|
|
- request_complete <= sdram_request_COMPLETE;
|
|
- else
|
|
- MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
|
|
- ram_chip_select <= start_request;
|
|
- request_complete <= ram_request_COMPLETE;
|
|
- end if;
|
|
end case;
|
|
else
|
|
+ sdram_chip_select <= '0';
|
|
+ ram_chip_select <= '0';
|
|
case addr_next(23 downto 21) is
|
|
when "000" =>
|
|
-- internal area for zpu, never happens!
|
|
Only in atari800core_v1_20140312_mist/: atari800core_assignment_defaults.qdf
|
|
diff -ur atari800core_v1_20140121_mcc216/atari800core.jdi atari800core_v1_20140312_mist/atari800core.jdi
|
|
--- atari800core_v1_20140121_mcc216/atari800core.jdi 2014-02-03 19:43:36.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/atari800core.jdi 2014-03-12 05:05:06.000000000 +0000
|
|
@@ -1,6 +1,62 @@
|
|
<sld_project_info>
|
|
<project>
|
|
- <hash md5_digest_80b="00000000000000000000"/>
|
|
+ <hash md5_digest_80b="7d0f11bf891bc55d775e"/>
|
|
</project>
|
|
<file_info/>
|
|
+ <hub_info ir_width="8" node_count="1"/>
|
|
+ <node_info>
|
|
+ <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
|
|
+ <parameters>
|
|
+ <parameter name="lpm_type" type="string" value="sld_signaltap"/>
|
|
+ <parameter name="sld_node_info" type="unknown" value="805334528"/>
|
|
+ <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
|
|
+ <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
|
|
+ <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
|
|
+ <parameter name="sld_data_bits" type="unknown" value="119"/>
|
|
+ <parameter name="sld_trigger_bits" type="unknown" value="119"/>
|
|
+ <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
|
|
+ <parameter name="sld_node_crc_hiword" type="unknown" value="37736"/>
|
|
+ <parameter name="sld_node_crc_loword" type="unknown" value="25945"/>
|
|
+ <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
|
|
+ <parameter name="sld_sample_depth" type="unknown" value="2048"/>
|
|
+ <parameter name="sld_segment_size" type="unknown" value="2048"/>
|
|
+ <parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
|
|
+ <parameter name="sld_state_bits" type="unknown" value="11"/>
|
|
+ <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
|
|
+ <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
|
|
+ <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
|
|
+ <parameter name="sld_trigger_level" type="unknown" value="1"/>
|
|
+ <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
|
|
+ <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
|
|
+ <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
|
|
+ <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
|
|
+ <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
|
|
+ <parameter name="sld_inversion_mask_length" type="unknown" value="382"/>
|
|
+ <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
|
|
+ <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
|
|
+ <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
|
|
+ <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
|
|
+ <parameter name="sld_current_resource_width" type="unknown" value="1"/>
|
|
+ <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
|
|
+ <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
|
|
+ <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
|
|
+ <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
|
|
+ <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
|
|
+ <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
|
|
+ <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
|
|
+ <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
|
|
+ </parameters>
|
|
+ <inputs/>
|
|
+ <outputs/>
|
|
+ </node>
|
|
+ </node_info>
|
|
</sld_project_info>
|
|
diff -ur atari800core_v1_20140121_mcc216/atari800core.qsf atari800core_v1_20140312_mist/atari800core.qsf
|
|
--- atari800core_v1_20140121_mcc216/atari800core.qsf 2014-02-03 19:39:52.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/atari800core.qsf 2014-03-12 05:08:27.000000000 +0000
|
|
@@ -1,6 +1,4 @@
|
|
-# -------------------------------------------------------------------------- #
|
|
-#
|
|
-# Copyright (C) 1991-2012 Altera Corporation
|
|
+# Copyright (C) 1991-2007 Altera Corporation
|
|
# Your use of Altera Corporation's design tools, logic functions
|
|
# and other software and tools, and its AMPP partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
@@ -13,287 +11,308 @@
|
|
# programming logic devices manufactured by Altera and sold by
|
|
# Altera or its authorized distributors. Please refer to the
|
|
# applicable agreement for further details.
|
|
-#
|
|
-# -------------------------------------------------------------------------- #
|
|
-#
|
|
-# Quartus II 64-Bit
|
|
-# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
|
|
-# Date created = 13:58:39 April 11, 2013
|
|
-#
|
|
-# -------------------------------------------------------------------------- #
|
|
-#
|
|
-# Notes:
|
|
-#
|
|
-# 1) The default values for assignments are stored in the file:
|
|
-# atari800core_assignment_defaults.qdf
|
|
-# If this file doesn't exist, see file:
|
|
+
|
|
+
|
|
+# The default values for assignments are stored in the file
|
|
+# minimig_de1_assignment_defaults.qdf
|
|
+# If this file doesn't exist, and for assignments not listed, see file
|
|
# assignment_defaults.qdf
|
|
-#
|
|
-# 2) Altera recommends that you do not modify this file. This
|
|
-# file is updated automatically by the Quartus II software
|
|
-# and any changes you make may be lost or overwritten.
|
|
-#
|
|
-# -------------------------------------------------------------------------- #
|
|
+
|
|
+# Altera recommends that you do not modify this file. This
|
|
+# file is updated automatically by the Quartus II software
|
|
+# and any changes you make may be lost or overwritten.
|
|
|
|
|
|
set_global_assignment -name FAMILY "Cyclone III"
|
|
-set_global_assignment -name DEVICE EP3C16E144C8
|
|
+set_global_assignment -name DEVICE EP3C25E144C8
|
|
set_global_assignment -name TOP_LEVEL_ENTITY atari800core
|
|
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
|
|
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39 APRIL 11, 2013"
|
|
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
|
|
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
|
|
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
|
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
|
|
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
|
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
|
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
|
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
|
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
|
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
|
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
|
|
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
|
+set_global_assignment -name GENERATE_RBF_FILE ON
|
|
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
|
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
|
+
|
|
+set_location_assignment PIN_7 -to LED
|
|
+set_location_assignment PIN_22 -to CLOCK_50[0]
|
|
+set_location_assignment PIN_23 -to CLOCK_50[1]
|
|
+set_location_assignment PIN_128 -to CLOCK_32[0]
|
|
+set_location_assignment PIN_129 -to CLOCK_32[1]
|
|
+set_location_assignment PIN_54 -to CLOCK_27[0]
|
|
+set_location_assignment PIN_55 -to CLOCK_27[1]
|
|
+set_location_assignment PIN_144 -to VGA_R[5]
|
|
+set_location_assignment PIN_143 -to VGA_R[4]
|
|
+set_location_assignment PIN_142 -to VGA_R[3]
|
|
+set_location_assignment PIN_141 -to VGA_R[2]
|
|
+set_location_assignment PIN_137 -to VGA_R[1]
|
|
set_location_assignment PIN_135 -to VGA_R[0]
|
|
-set_location_assignment PIN_134 -to VGA_R[1]
|
|
-set_location_assignment PIN_133 -to VGA_R[2]
|
|
-set_location_assignment PIN_132 -to VGA_R[3]
|
|
-set_location_assignment PIN_141 -to VGA_G[0]
|
|
-set_location_assignment PIN_142 -to VGA_G[1]
|
|
-set_location_assignment PIN_143 -to VGA_G[2]
|
|
-set_location_assignment PIN_144 -to VGA_G[3]
|
|
-set_location_assignment PIN_4 -to VGA_B[0]
|
|
-set_location_assignment PIN_7 -to VGA_B[1]
|
|
-set_location_assignment PIN_10 -to VGA_B[2]
|
|
-set_location_assignment PIN_11 -to VGA_B[3]
|
|
-set_location_assignment PIN_136 -to VGA_HS
|
|
-set_location_assignment PIN_137 -to VGA_VS
|
|
+set_location_assignment PIN_133 -to VGA_B[5]
|
|
+set_location_assignment PIN_132 -to VGA_B[4]
|
|
+set_location_assignment PIN_125 -to VGA_B[3]
|
|
+set_location_assignment PIN_121 -to VGA_B[2]
|
|
+set_location_assignment PIN_120 -to VGA_B[1]
|
|
+set_location_assignment PIN_115 -to VGA_B[0]
|
|
+set_location_assignment PIN_114 -to VGA_G[5]
|
|
+set_location_assignment PIN_113 -to VGA_G[4]
|
|
+set_location_assignment PIN_112 -to VGA_G[3]
|
|
+set_location_assignment PIN_111 -to VGA_G[2]
|
|
+set_location_assignment PIN_110 -to VGA_G[1]
|
|
+set_location_assignment PIN_106 -to VGA_G[0]
|
|
+set_location_assignment PIN_136 -to VGA_VS
|
|
+set_location_assignment PIN_119 -to VGA_HS
|
|
+set_location_assignment PIN_65 -to AUDIO_L
|
|
+set_location_assignment PIN_80 -to AUDIO_R
|
|
+set_location_assignment PIN_46 -to UART_TX
|
|
+set_location_assignment PIN_31 -to UART_RX
|
|
+set_location_assignment PIN_105 -to SPI_DO
|
|
+set_location_assignment PIN_88 -to SPI_DI
|
|
+set_location_assignment PIN_126 -to SPI_SCK
|
|
+set_location_assignment PIN_127 -to SPI_SS2
|
|
+set_location_assignment PIN_91 -to SPI_SS3
|
|
+set_location_assignment PIN_90 -to SPI_SS4
|
|
+set_location_assignment PIN_13 -to CONF_DATA0
|
|
+
|
|
+set_location_assignment PIN_49 -to SDRAM_A[0]
|
|
+set_location_assignment PIN_44 -to SDRAM_A[1]
|
|
+set_location_assignment PIN_42 -to SDRAM_A[2]
|
|
+set_location_assignment PIN_39 -to SDRAM_A[3]
|
|
+set_location_assignment PIN_4 -to SDRAM_A[4]
|
|
+set_location_assignment PIN_6 -to SDRAM_A[5]
|
|
+set_location_assignment PIN_8 -to SDRAM_A[6]
|
|
+set_location_assignment PIN_10 -to SDRAM_A[7]
|
|
+set_location_assignment PIN_11 -to SDRAM_A[8]
|
|
+set_location_assignment PIN_28 -to SDRAM_A[9]
|
|
+set_location_assignment PIN_50 -to SDRAM_A[10]
|
|
+set_location_assignment PIN_30 -to SDRAM_A[11]
|
|
+set_location_assignment PIN_32 -to SDRAM_A[12]
|
|
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
|
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
|
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
|
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
|
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
|
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
|
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
|
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
|
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
|
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
|
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
|
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
|
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
|
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
|
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
|
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
|
+set_location_assignment PIN_58 -to SDRAM_BA[0]
|
|
+set_location_assignment PIN_51 -to SDRAM_BA[1]
|
|
+set_location_assignment PIN_85 -to SDRAM_DQMH
|
|
+set_location_assignment PIN_67 -to SDRAM_DQML
|
|
+set_location_assignment PIN_60 -to SDRAM_nRAS
|
|
+set_location_assignment PIN_64 -to SDRAM_nCAS
|
|
+set_location_assignment PIN_66 -to SDRAM_nWE
|
|
+set_location_assignment PIN_59 -to SDRAM_nCS
|
|
+set_location_assignment PIN_33 -to SDRAM_CKE
|
|
+set_location_assignment PIN_43 -to SDRAM_CLK
|
|
+
|
|
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
|
|
+set_global_assignment -name SMART_RECOMPILE ON
|
|
set_global_assignment -name ENABLE_SIGNALTAP ON
|
|
-set_location_assignment PIN_44 -to SD_CLK
|
|
-set_location_assignment PIN_46 -to SD_CMD
|
|
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
|
+set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
|
|
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
|
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
|
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
|
|
+set_global_assignment -name TPD_REQUIREMENT "2 ns"
|
|
+set_global_assignment -name TSU_REQUIREMENT "2 ns"
|
|
+set_global_assignment -name TCO_REQUIREMENT "2 ns"
|
|
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
|
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
|
-set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
|
|
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
|
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
|
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
|
|
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
|
|
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
|
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
|
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
|
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
|
|
+set_global_assignment -name MISC_FILE atari800core.dpf
|
|
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
+
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
|
|
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
|
|
+
|
|
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
|
|
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
|
|
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
|
|
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
|
|
+
|
|
+#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
|
|
+#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
|
|
+
|
|
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
|
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
|
-set_global_assignment -name SMART_RECOMPILE ON
|
|
-set_global_assignment -name ENABLE_DRC_SETTINGS ON
|
|
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
|
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
|
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
|
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
|
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
|
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
|
|
-set_global_assignment -name FITTER_EFFORT "AUTO FIT"
|
|
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
|
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
|
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
|
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
|
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
|
|
|
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
|
|
-set_location_assignment PIN_28 -to AUDIO_L
|
|
-set_location_assignment PIN_30 -to AUDIO_R
|
|
-set_location_assignment PIN_53 -to CPU_RESET_n
|
|
-set_location_assignment PIN_55 -to FPGA_CLK
|
|
-set_location_assignment PIN_127 -to JOY1_n[0]
|
|
-set_location_assignment PIN_91 -to JOY1_n[1]
|
|
-set_location_assignment PIN_90 -to JOY1_n[2]
|
|
-set_location_assignment PIN_88 -to JOY1_n[3]
|
|
-set_location_assignment PIN_89 -to JOY1_n[4]
|
|
-set_location_assignment PIN_126 -to JOY1_n[5]
|
|
-set_location_assignment PIN_128 -to JOY2_n[0]
|
|
-set_location_assignment PIN_25 -to JOY2_n[1]
|
|
-set_location_assignment PIN_24 -to JOY2_n[2]
|
|
-set_location_assignment PIN_22 -to JOY2_n[3]
|
|
-set_location_assignment PIN_23 -to JOY2_n[4]
|
|
-set_location_assignment PIN_129 -to JOY2_n[5]
|
|
-set_location_assignment PIN_33 -to PS2K_DAT
|
|
-set_location_assignment PIN_39 -to PS2K_CLK
|
|
-set_location_assignment PIN_32 -to PS2M_DAT
|
|
-set_location_assignment PIN_31 -to PS2M_CLK
|
|
-set_location_assignment PIN_52 -to SD_DAT0
|
|
-set_location_assignment PIN_49 -to SD_DAT3
|
|
-set_location_assignment PIN_42 -to USB_P
|
|
-set_location_assignment PIN_43 -to USB_N
|
|
-set_location_assignment PIN_50 -to USB2_P
|
|
-set_location_assignment PIN_51 -to USB2_N
|
|
-set_location_assignment PIN_112 -to SDRAM_CLK
|
|
-set_location_assignment PIN_61 -to SDRAM_A[0]
|
|
-set_location_assignment PIN_60 -to SDRAM_A[1]
|
|
-set_location_assignment PIN_59 -to SDRAM_A[2]
|
|
-set_location_assignment PIN_58 -to SDRAM_A[3]
|
|
-set_location_assignment PIN_125 -to SDRAM_A[4]
|
|
-set_location_assignment PIN_121 -to SDRAM_A[5]
|
|
-set_location_assignment PIN_120 -to SDRAM_A[6]
|
|
-set_location_assignment PIN_119 -to SDRAM_A[7]
|
|
-set_location_assignment PIN_115 -to SDRAM_A[8]
|
|
-set_location_assignment PIN_114 -to SDRAM_A[9]
|
|
-set_location_assignment PIN_64 -to SDRAM_A[10]
|
|
-set_location_assignment PIN_113 -to SDRAM_A[11]
|
|
-set_location_assignment PIN_111 -to SDRAM_A[12]
|
|
-set_location_assignment PIN_66 -to SDRAM_BA[0]
|
|
-set_location_assignment PIN_65 -to SDRAM_BA[1]
|
|
-set_location_assignment PIN_87 -to SDRAM_DQ[0]
|
|
-set_location_assignment PIN_86 -to SDRAM_DQ[1]
|
|
-set_location_assignment PIN_85 -to SDRAM_DQ[2]
|
|
-set_location_assignment PIN_83 -to SDRAM_DQ[3]
|
|
-set_location_assignment PIN_80 -to SDRAM_DQ[4]
|
|
-set_location_assignment PIN_79 -to SDRAM_DQ[5]
|
|
-set_location_assignment PIN_77 -to SDRAM_DQ[6]
|
|
-set_location_assignment PIN_76 -to SDRAM_DQ[7]
|
|
-set_location_assignment PIN_106 -to SDRAM_DQ[8]
|
|
-set_location_assignment PIN_105 -to SDRAM_DQ[9]
|
|
-set_location_assignment PIN_104 -to SDRAM_DQ[10]
|
|
-set_location_assignment PIN_103 -to SDRAM_DQ[11]
|
|
-set_location_assignment PIN_101 -to SDRAM_DQ[12]
|
|
-set_location_assignment PIN_100 -to SDRAM_DQ[13]
|
|
-set_location_assignment PIN_99 -to SDRAM_DQ[14]
|
|
-set_location_assignment PIN_98 -to SDRAM_DQ[15]
|
|
-set_location_assignment PIN_67 -to SDRAM_CS_n
|
|
-set_location_assignment PIN_68 -to SDRAM_RAS_n
|
|
-set_location_assignment PIN_69 -to SDRAM_CAS_n
|
|
-set_location_assignment PIN_71 -to SDRAM_WE_n
|
|
-set_location_assignment PIN_6 -to CFG_DOUT
|
|
-set_location_assignment PIN_8 -to CFG_CS_n
|
|
-set_location_assignment PIN_12 -to CFG_CLK
|
|
-set_location_assignment PIN_13 -to CFG_DIN
|
|
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
|
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
|
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
|
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
-set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
|
|
-set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN
|
|
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
|
|
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
|
|
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
|
|
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
|
|
-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
|
|
-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
|
|
|
|
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
|
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
|
+
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
|
|
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
|
|
+
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
|
|
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
|
|
+
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
|
|
+
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
|
|
+
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
|
|
+
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
|
|
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
|
|
+
|
|
+
|
|
+set_global_assignment -name VHDL_FILE data_io.vhdl
|
|
+set_global_assignment -name QIP_FILE basic.qip
|
|
+set_global_assignment -name VERILOG_FILE user_io.v
|
|
set_global_assignment -name VERILOG_FILE hq_dac.v
|
|
set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
|
|
-set_global_assignment -name VHDL_FILE romlo.vhd
|
|
-set_global_assignment -name VHDL_FILE romhi.vhd
|
|
set_global_assignment -name VHDL_FILE ramint.vhd
|
|
set_global_assignment -name VHDL_FILE atari800core.vhd
|
|
set_global_assignment -name VHDL_FILE spi_master.vhd
|
|
@@ -307,7 +326,6 @@
|
|
set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
|
|
set_global_assignment -name VHDL_FILE cpu.vhd
|
|
set_global_assignment -name QIP_FILE pll.qip
|
|
-set_global_assignment -name SDC_FILE atari800core.sdc
|
|
set_global_assignment -name VHDL_FILE reg_file.vhdl
|
|
set_global_assignment -name VHDL_FILE address_decoder.vhdl
|
|
set_global_assignment -name VHDL_FILE pokey.vhdl
|
|
@@ -345,4 +363,272 @@
|
|
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
|
|
set_global_assignment -name VHDL_FILE internalromram.vhd
|
|
set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
|
|
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
|
|
+set_global_assignment -name SDC_FILE atari800core.sdc
|
|
+set_global_assignment -name QIP_FILE rom16.qip
|
|
+set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
|
|
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SPI_DI -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SPI_DO -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SPI_SS2 -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "data_io:mist_spi_interface|SPI_CLK" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
|
|
+set_global_assignment -name QIP_FILE mist_sector_buffer.qip
|
|
+set_global_assignment -name VHDL_FILE covox.vhd
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SPI_DI -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SPI_DO -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SPI_SS2 -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
|
|
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=119" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=119" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=382" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=25945" -section_id auto_signaltap_0
|
|
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=37736" -section_id auto_signaltap_0
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
|
\ No newline at end of file
|
|
Binary files atari800core_v1_20140121_mcc216/atari800core.qws and atari800core_v1_20140312_mist/atari800core.qws differ
|
|
diff -ur atari800core_v1_20140121_mcc216/atari800core.sdc atari800core_v1_20140312_mist/atari800core.sdc
|
|
--- atari800core_v1_20140121_mcc216/atari800core.sdc 2014-01-21 19:27:45.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/atari800core.sdc 2014-02-16 08:53:36.000000000 +0000
|
|
@@ -1,3 +1,3 @@
|
|
-create_clock -period 5MHz [get_ports FPGA_CLK]
|
|
+create_clock -period 27MHz [get_ports CLOCK_27[0]]
|
|
derive_pll_clocks
|
|
derive_clock_uncertainty
|
|
\ No newline at end of file
|
|
diff -ur atari800core_v1_20140121_mcc216/atari800core.vhd atari800core_v1_20140312_mist/atari800core.vhd
|
|
--- atari800core_v1_20140121_mcc216/atari800core.vhd 2014-01-28 20:47:59.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/atari800core.vhd 2014-03-12 05:00:20.000000000 +0000
|
|
@@ -18,49 +18,155 @@
|
|
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
+use ieee.numeric_std.all;
|
|
|
|
LIBRARY work;
|
|
|
|
ENTITY atari800core IS
|
|
PORT
|
|
(
|
|
- FPGA_CLK : IN STD_LOGIC;
|
|
- PS2K_CLK : IN STD_LOGIC;
|
|
- PS2K_DAT : IN STD_LOGIC;
|
|
- PS2M_CLK : IN STD_LOGIC;
|
|
- PS2M_DAT : IN STD_LOGIC;
|
|
+ CLOCK_27 : IN STD_LOGIC_VECTOR(1 downto 0);
|
|
+-- PS2K_CLK : IN STD_LOGIC;
|
|
+-- PS2K_DAT : IN STD_LOGIC;
|
|
+-- PS2M_CLK : IN STD_LOGIC;
|
|
+-- PS2M_DAT : IN STD_LOGIC;
|
|
|
|
VGA_VS : OUT STD_LOGIC;
|
|
VGA_HS : OUT STD_LOGIC;
|
|
- VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
- VGA_G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
- VGA_R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
+ VGA_B : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+ VGA_G : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+ VGA_R : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
|
|
- JOY1_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
- JOY2_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+-- JOY1_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+-- JOY2_n : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
|
|
AUDIO_L : OUT std_logic;
|
|
AUDIO_R : OUT std_logic;
|
|
|
|
SDRAM_BA : OUT STD_LOGIC_VECTOR(1 downto 0);
|
|
- SDRAM_CS_N : OUT STD_LOGIC;
|
|
- SDRAM_RAS_N : OUT STD_LOGIC;
|
|
- SDRAM_CAS_N : OUT STD_LOGIC;
|
|
- SDRAM_WE_N : OUT STD_LOGIC;
|
|
- SDRAM_DQM_n : OUT STD_LOGIC_vector(1 downto 0);
|
|
+ SDRAM_nCS : OUT STD_LOGIC;
|
|
+ SDRAM_nRAS : OUT STD_LOGIC;
|
|
+ SDRAM_nCAS : OUT STD_LOGIC;
|
|
+ SDRAM_nWE : OUT STD_LOGIC;
|
|
+ SDRAM_DQMH : OUT STD_LOGIC;
|
|
+ SDRAM_DQML : OUT STD_LOGIC;
|
|
SDRAM_CLK : OUT STD_LOGIC;
|
|
- --SDRAM_CKE : OUT STD_LOGIC;
|
|
+ SDRAM_CKE : OUT STD_LOGIC;
|
|
SDRAM_A : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
|
|
SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
|
|
- SD_DAT0 : IN STD_LOGIC;
|
|
- SD_CLK : OUT STD_LOGIC;
|
|
- SD_CMD : OUT STD_LOGIC;
|
|
- SD_DAT3 : OUT STD_LOGIC
|
|
+-- SD_DAT0 : IN STD_LOGIC;
|
|
+-- SD_CLK : OUT STD_LOGIC;
|
|
+-- SD_CMD : OUT STD_LOGIC;
|
|
+-- SD_DAT3 : OUT STD_LOGIC
|
|
+
|
|
+ LED : OUT std_logic;
|
|
+
|
|
+ UART_TX : OUT STD_LOGIC;
|
|
+ UART_RX : IN STD_LOGIC;
|
|
+
|
|
+ SPI_DO : INOUT STD_LOGIC;
|
|
+ SPI_DI : IN STD_LOGIC;
|
|
+ SPI_SCK : IN STD_LOGIC;
|
|
+ SPI_SS2 : IN STD_LOGIC;
|
|
+ SPI_SS3 : IN STD_LOGIC;
|
|
+ SPI_SS4 : IN STD_LOGIC;
|
|
+ CONF_DATA0 : IN STD_LOGIC -- AKA SPI_SS5
|
|
);
|
|
END atari800core;
|
|
|
|
ARCHITECTURE bdf_type OF atari800core IS
|
|
+--
|
|
+--component generic_ram_infer IS
|
|
+-- generic
|
|
+-- (
|
|
+-- ADDRESS_WIDTH : natural := 9;
|
|
+-- SPACE : natural := 512;
|
|
+-- DATA_WIDTH : natural := 8
|
|
+-- );
|
|
+-- PORT
|
|
+-- (
|
|
+-- clock: IN std_logic;
|
|
+-- data: IN std_logic_vector (data_width-1 DOWNTO 0);
|
|
+-- address: IN std_logic_vector(address_width-1 downto 0);
|
|
+-- we: IN std_logic;
|
|
+-- q: OUT std_logic_vector (data_width-1 DOWNTO 0)
|
|
+-- );
|
|
+--END component;
|
|
+
|
|
+component mist_sector_buffer IS
|
|
+ PORT
|
|
+ (
|
|
+ address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
|
|
+ address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
|
|
+ clock_a : IN STD_LOGIC := '1';
|
|
+ clock_b : IN STD_LOGIC ;
|
|
+ data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
|
+ data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
|
+ wren_a : IN STD_LOGIC := '0';
|
|
+ wren_b : IN STD_LOGIC := '0';
|
|
+ q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
|
+ q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
|
+ );
|
|
+END component;
|
|
+
|
|
+component synchronizer IS
|
|
+PORT
|
|
+(
|
|
+ CLK : IN STD_LOGIC;
|
|
+ RAW : IN STD_LOGIC;
|
|
+ SYNC : OUT STD_LOGIC
|
|
+);
|
|
+END component;
|
|
+
|
|
+component data_io IS
|
|
+ PORT
|
|
+ (
|
|
+ CLK : in std_logic;
|
|
+ RESET_n : in std_logic;
|
|
+
|
|
+ -- SPI connection - up to upstream to make miso 'Z' on ss_io going high
|
|
+ SPI_CLK : in std_logic;
|
|
+ SPI_SS_IO : in std_logic;
|
|
+ SPI_MISO: out std_logic;
|
|
+ SPI_MOSI : in std_logic;
|
|
+
|
|
+ -- Sector access request
|
|
+ request : in std_logic;
|
|
+ sector : in std_logic_vector(23 downto 0);
|
|
+ ready : out std_logic;
|
|
+
|
|
+ -- DMA to RAM
|
|
+ ADDR: out std_logic_vector(8 downto 0);
|
|
+ DATA_OUT : out std_logic_vector(7 downto 0);
|
|
+ DATA_IN : in std_logic_vector(7 downto 0);
|
|
+ WR_EN : out std_logic
|
|
+ );
|
|
+end component;
|
|
+
|
|
+component user_io
|
|
+ PORT(
|
|
+ SPI_CLK : in std_logic;
|
|
+ SPI_SS_IO : in std_logic;
|
|
+ SPI_MISO : out std_logic;
|
|
+ SPI_MOSI : in std_logic;
|
|
+ CORE_TYPE : in std_logic_vector(7 downto 0);
|
|
+ JOY0 : out std_logic_vector(5 downto 0);
|
|
+ JOY1 : out std_logic_vector(5 downto 0);
|
|
+ KEYBOARD : out std_logic_vector(127 downto 0);
|
|
+ BUTTONS : out std_logic_vector(1 downto 0);
|
|
+ SWITCHES : out std_logic_vector(1 downto 0)
|
|
+ );
|
|
+end component;
|
|
+
|
|
+COMPONENT complete_address_decoder IS
|
|
+generic (width : natural := 1);
|
|
+PORT
|
|
+(
|
|
+ addr_in : in std_logic_vector(width-1 downto 0);
|
|
+ addr_decoded : out std_logic_vector((2**width)-1 downto 0)
|
|
+);
|
|
+END component;
|
|
|
|
COMPONENT cpu
|
|
PORT(CLK : IN STD_LOGIC;
|
|
@@ -151,6 +257,8 @@
|
|
CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
+ COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
|
|
+ COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
|
|
CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
|
);
|
|
@@ -177,6 +285,7 @@
|
|
ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
+ ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
MEMORY_FETCH : OUT STD_LOGIC;
|
|
ZPU_READ_ENABLE : OUT STD_LOGIC;
|
|
ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
|
|
@@ -328,9 +437,11 @@
|
|
CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
- ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
+ ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
|
ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
- rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
+ rom_select : in std_logic_vector(5 downto 0);
|
|
+ cart_select : in std_logic_vector(6 downto 0);
|
|
+ cart_activate : in std_logic;
|
|
SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
|
|
ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
@@ -363,7 +474,8 @@
|
|
RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
|
|
ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
|
|
SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
|
|
- WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
|
+ WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
+ D6_WR_ENABLE : out std_logic
|
|
);
|
|
END COMPONENT;
|
|
|
|
@@ -386,7 +498,7 @@
|
|
ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
|
|
DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
- REPLY : OUT STD_LOGIC;
|
|
+ COMPLETE : OUT STD_LOGIC;
|
|
SDRAM_BA0 : OUT STD_LOGIC;
|
|
SDRAM_BA1 : OUT STD_LOGIC;
|
|
SDRAM_CKE : OUT STD_LOGIC;
|
|
@@ -509,10 +621,13 @@
|
|
DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
|
|
- RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
- ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
+ RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
+ ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
- ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
|
+ ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
+ sector : out std_logic_vector(31 downto 0);
|
|
+ sector_request : out std_logic;
|
|
+ sector_ready : in std_logic
|
|
);
|
|
END COMPONENT;
|
|
|
|
@@ -581,6 +696,20 @@
|
|
);
|
|
END component;
|
|
|
|
+component covox IS
|
|
+PORT
|
|
+(
|
|
+ CLK : IN STD_LOGIC;
|
|
+ ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
+ DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
+ WR_EN : IN STD_LOGIC;
|
|
+
|
|
+ covox_channel0 : out std_logic_vector(7 downto 0);
|
|
+ covox_channel1 : out std_logic_vector(7 downto 0);
|
|
+ covox_channel2 : out std_logic_vector(7 downto 0);
|
|
+ covox_channel3 : out std_logic_vector(7 downto 0)
|
|
+);
|
|
+END component;
|
|
|
|
SIGNAL ANTIC_ADDR : STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
SIGNAL ANTIC_AN : STD_LOGIC_VECTOR(2 DOWNTO 0);
|
|
@@ -642,7 +771,7 @@
|
|
SIGNAL GTIA_SOUND : STD_LOGIC;
|
|
SIGNAL GTIA_WRITE_ENABLE : STD_LOGIC;
|
|
SIGNAL IRQ_n : STD_LOGIC;
|
|
-SIGNAL KBCODE : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
+SIGNAL KBCODE_DUMMY : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
SIGNAL KEY_HELD : STD_LOGIC;
|
|
SIGNAL KEY_INTERRUPT : STD_LOGIC;
|
|
SIGNAL KEYBOARD_RESPONSE : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
@@ -682,14 +811,14 @@
|
|
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
|
|
SIGNAL RAM_REQUEST : STD_LOGIC;
|
|
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
|
|
-SIGNAL RAM_SELECT : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
+SIGNAL RAM_SELECT : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
|
|
SIGNAL RESET_N : STD_LOGIC;
|
|
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
|
|
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
SIGNAL ROM_REQUEST : STD_LOGIC;
|
|
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
|
|
-SIGNAL ROM_SELECT : STD_LOGIC_VECTOR(1 DOWNTO 0);
|
|
+SIGNAL ROM_SELECT : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
SIGNAL SCANDOUBLER_SHARED_ENABLE_HIGH : STD_LOGIC;
|
|
SIGNAL SCANDOUBLER_SHARED_ENABLE_LOW : STD_LOGIC;
|
|
SIGNAL SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
|
|
@@ -733,6 +862,7 @@
|
|
SIGNAL ZPU_READ_ENABLE : STD_LOGIC;
|
|
SIGNAL ZPU_RESET : STD_LOGIC;
|
|
SIGNAL ZPU_ROM_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
+SIGNAL ZPU_SECTOR_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
SIGNAL ZPU_STACK_WRITE : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
|
|
@@ -754,10 +884,344 @@
|
|
SIGNAL LEDG_dummy : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
|
signal UART_TXD_dummy : std_logic;
|
|
|
|
+-- STUB OUT FOR NOW
|
|
+SIGNAL PS2K_CLK : STD_LOGIC;
|
|
+SIGNAL PS2K_DAT : STD_LOGIC;
|
|
+signal JOY1_n : STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+signal JOY2_n : STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+signal JOY1 : STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+signal JOY2 : STD_LOGIC_VECTOR(5 DOWNTO 0);
|
|
+
|
|
+
|
|
+SIGNAL SD_DAT0 : STD_LOGIC;
|
|
+SIGNAL SD_CLK : STD_LOGIC;
|
|
+SIGNAL SD_CMD : STD_LOGIC;
|
|
+SIGNAL SD_DAT3 : STD_LOGIC;
|
|
+
|
|
+signal mist_buttons : std_logic_vector(1 downto 0);
|
|
+signal mist_switches : std_logic_vector(1 downto 0);
|
|
+
|
|
+signal keyboard : std_logic_vector(127 downto 0);
|
|
+signal atari_keyboard : std_logic_vector(63 downto 0);
|
|
+
|
|
+SIGNAL SHIFT_PRESSED_DUMMY : STD_LOGIC;
|
|
+SIGNAL BREAK_PRESSED_DUMMY : STD_LOGIC;
|
|
+SIGNAL CONTROL_PRESSED : STD_LOGIC;
|
|
+
|
|
+SIGNAL CONSOL_OPTION_DUMMY : STD_LOGIC;
|
|
+SIGNAL CONSOL_SELECT_DUMMY : STD_LOGIC;
|
|
+SIGNAL CONSOL_START_DUMMY : STD_LOGIC;
|
|
+
|
|
+signal capslock_pressed : std_logic;
|
|
+signal capsheld_next : std_logic;
|
|
+signal capsheld_reg : std_logic;
|
|
+
|
|
+signal mist_sector_ready : std_logic;
|
|
+signal mist_sector_ready_sync : std_logic;
|
|
+signal mist_sector_request : std_logic;
|
|
+signal mist_sector_request_sync : std_logic;
|
|
+signal mist_sector : std_logic_vector(31 downto 0);
|
|
+signal mist_sector_sync : std_logic_vector(31 downto 0);
|
|
+
|
|
+
|
|
+signal mist_addr : std_logic_vector(8 downto 0);
|
|
+signal mist_do : std_logic_vector(7 downto 0);
|
|
+signal mist_di : std_logic_vector(7 downto 0);
|
|
+signal mist_wren : std_logic;
|
|
+
|
|
+signal spi_miso_data : std_logic;
|
|
+signal spi_miso_io : std_logic;
|
|
+
|
|
+signal covox_write_enable : std_logic;
|
|
+signal covox_channel0 : std_logic_vector(7 downto 0);
|
|
+signal covox_channel1 : std_logic_vector(7 downto 0);
|
|
+signal covox_channel2 : std_logic_vector(7 downto 0);
|
|
+signal covox_channel3 : std_logic_vector(7 downto 0);
|
|
+
|
|
BEGIN
|
|
|
|
+
|
|
+-- mist spi io
|
|
+mist_spi_interface : data_io
|
|
+ PORT map
|
|
+ (
|
|
+ CLK =>spi_sck,
|
|
+ RESET_n =>reset_n,
|
|
+
|
|
+ -- SPI connection - up to upstream to make miso 'Z' on ss_io going high
|
|
+ SPI_CLK =>spi_sck,
|
|
+ SPI_SS_IO => spi_ss2,
|
|
+ SPI_MISO => spi_miso_data,
|
|
+ SPI_MOSI => spi_di,
|
|
+
|
|
+ -- Sector access request
|
|
+ request => mist_sector_request_sync,
|
|
+ sector => mist_sector_sync(23 downto 0),
|
|
+ ready => mist_sector_ready,
|
|
+
|
|
+ -- DMA to RAM
|
|
+ ADDR => mist_addr,
|
|
+ DATA_OUT => mist_do,
|
|
+ DATA_IN => mist_di,
|
|
+ WR_EN => mist_wren
|
|
+ );
|
|
+
|
|
+ select_sync : synchronizer
|
|
+ PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
|
|
+
|
|
+ select_sync2 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
|
|
+
|
|
+ sector_sync0 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
|
|
+
|
|
+ sector_sync1 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
|
|
+
|
|
+ sector_sync2 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
|
|
+
|
|
+ sector_sync3 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
|
|
+
|
|
+ sector_sync4 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
|
|
+
|
|
+ sector_sync5 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
|
|
+
|
|
+ sector_sync6 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
|
|
+
|
|
+ sector_sync7 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
|
|
+
|
|
+ sector_sync8 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
|
|
+
|
|
+ sector_sync9 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
|
|
+
|
|
+ sector_sync10 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
|
|
+
|
|
+ sector_sync11 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
|
|
+
|
|
+ sector_sync12 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
|
|
+
|
|
+ sector_sync13 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
|
|
+
|
|
+ sector_sync14 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
|
|
+
|
|
+ sector_sync15 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
|
|
+
|
|
+ sector_sync16 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
|
|
+
|
|
+ sector_sync17 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
|
|
|
|
+ sector_sync18 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
|
|
+
|
|
+ sector_sync19 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
|
|
+
|
|
+ sector_sync20 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
|
|
+
|
|
+ sector_sync21 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
|
|
+
|
|
+ sector_sync22 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
|
|
+
|
|
+ sector_sync23 : synchronizer
|
|
+ PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
|
|
+
|
|
+
|
|
+ spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
|
|
+
|
|
+ -- TODO, dual port, dual clock!
|
|
+-- mist_sector_buffer : generic_ram_infer
|
|
+-- generic map
|
|
+-- (
|
|
+-- ADDRESS_WIDTH => 9,
|
|
+-- SPACE => 512,
|
|
+-- DATA_WIDTH => 8
|
|
+-- )
|
|
+-- PORT map
|
|
+-- (
|
|
+-- clock => spi_sck,
|
|
+-- data => mist_do,
|
|
+-- address => mist_addr,
|
|
+-- we => mist_wren,
|
|
+-- q => mist_di
|
|
+-- );
|
|
+
|
|
+mist_sector_buffer1 : mist_sector_buffer
|
|
+ PORT map
|
|
+ (
|
|
+ address_a => mist_addr,
|
|
+ address_b => ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
|
|
+ clock_a => spi_sck,
|
|
+ clock_b => clk,
|
|
+ data_a => mist_do,
|
|
+ data_b => zpu_do,
|
|
+ wren_a => mist_wren,
|
|
+ wren_b => '0',
|
|
+ q_a => mist_di,
|
|
+ q_b => zpu_sector_data
|
|
+ );
|
|
+
|
|
+my_user_io : user_io
|
|
+ PORT map(
|
|
+ SPI_CLK => SPI_SCK,
|
|
+ SPI_SS_IO => CONF_DATA0,
|
|
+ SPI_MISO => SPI_miso_io,
|
|
+ SPI_MOSI => SPI_DI,
|
|
+ CORE_TYPE => x"A4",
|
|
+ JOY0 => joy1,
|
|
+ JOY1 => joy2,
|
|
+ KEYBOARD => keyboard,
|
|
+ BUTTONS => mist_buttons,
|
|
+ SWITCHES => mist_switches
|
|
+ );
|
|
+
|
|
+ joy1_n <= not(joy1);
|
|
+ joy2_n <= not(joy2);
|
|
+
|
|
+ process(clk,reset_n)
|
|
+ begin
|
|
+ if (reset_n='0') then
|
|
+ capsheld_reg <= '0';
|
|
+ elsif (clk'event and clk='1') then
|
|
+ capsheld_reg <= capsheld_next;
|
|
+ end if;
|
|
+ end process;
|
|
+
|
|
+ process(keyboard,capsheld_reg)
|
|
+ begin
|
|
+ capsheld_next <= capsheld_reg;
|
|
+ capslock_pressed <= '0';
|
|
+
|
|
+ if ((keyboard(58) xor capsheld_reg)='1') then
|
|
+ capsheld_next <= keyboard(58);
|
|
+
|
|
+ -- assert something for 10 frames
|
|
+ capslock_pressed <= '1';
|
|
+ end if;
|
|
+ end process;
|
|
+
|
|
+atari_keyboard(63) <= keyboard(30);
|
|
+atari_keyboard(62) <= keyboard(31);
|
|
+atari_keyboard(61) <= keyboard(34);
|
|
+atari_keyboard(60) <= '0';
|
|
+atari_keyboard(58) <= keyboard(32);
|
|
+atari_keyboard(57) <= keyboard(35);
|
|
+atari_keyboard(56) <= keyboard(33);
|
|
+atari_keyboard(55) <= keyboard(13);
|
|
+atari_keyboard(54) <= keyboard(12);
|
|
+atari_keyboard(53) <= keyboard(9);
|
|
+atari_keyboard(52) <= keyboard(14);
|
|
+atari_keyboard(51) <= keyboard(8);
|
|
+atari_keyboard(50) <= keyboard(11);
|
|
+atari_keyboard(48) <= keyboard(10);
|
|
+atari_keyboard(47) <= keyboard(16);
|
|
+atari_keyboard(46) <= keyboard(17);
|
|
+atari_keyboard(45) <= keyboard(20);
|
|
+atari_keyboard(44) <= keyboard(15);
|
|
+atari_keyboard(43) <= keyboard(21);
|
|
+atari_keyboard(42) <= keyboard(18);
|
|
+atari_keyboard(40) <= keyboard(19);
|
|
+atari_keyboard(39) <= keyboard(56);
|
|
+atari_keyboard(38) <= keyboard(53);
|
|
+atari_keyboard(37) <= keyboard(50);
|
|
+atari_keyboard(35) <= keyboard(49);
|
|
+atari_keyboard(34) <= keyboard(52);
|
|
+atari_keyboard(33) <= keyboard(57);
|
|
+atari_keyboard(32) <= keyboard(51);
|
|
+atari_keyboard(31) <= keyboard(2);
|
|
+atari_keyboard(30) <= keyboard(3);
|
|
+atari_keyboard(29) <= keyboard(6);
|
|
+atari_keyboard(28) <= keyboard(1);
|
|
+atari_keyboard(27) <= keyboard(7);
|
|
+atari_keyboard(26) <= keyboard(4);
|
|
+atari_keyboard(24) <= keyboard(5);
|
|
+atari_keyboard(23) <= keyboard(44);
|
|
+atari_keyboard(22) <= keyboard(45);
|
|
+atari_keyboard(21) <= keyboard(48);
|
|
+atari_keyboard(18) <= keyboard(46);
|
|
+atari_keyboard(17) <= keyboard(59);
|
|
+atari_keyboard(16) <= keyboard(47);
|
|
+atari_keyboard(15) <= keyboard(27);
|
|
+atari_keyboard(14) <= keyboard(26);
|
|
+atari_keyboard(13) <= keyboard(23);
|
|
+atari_keyboard(12) <= keyboard(28);
|
|
+atari_keyboard(11) <= keyboard(22);
|
|
+atari_keyboard(10) <= keyboard(25);
|
|
+atari_keyboard(8) <= keyboard(24);
|
|
+atari_keyboard(7) <= keyboard(41);
|
|
+atari_keyboard(6) <= keyboard(40);
|
|
+atari_keyboard(5) <= keyboard(37);
|
|
+atari_keyboard(2) <= keyboard(39);
|
|
+atari_keyboard(1) <= keyboard(36);
|
|
+atari_keyboard(0) <= keyboard(38);
|
|
+
|
|
+
|
|
+shift_pressed <= keyboard(54) or keyboard(42);
|
|
+control_pressed <= keyboard(29);
|
|
+break_pressed <= keyboard(96); -- TODO - not on st keyboard
|
|
+
|
|
+consol_start <= keyboard(60); --F2
|
|
+consol_select <= keyboard(61); --F3
|
|
+consol_option <= keyboard(62); -- F4
|
|
+
|
|
+--f5 <= keyboard(63);
|
|
+--f6 <= keyboard(64);
|
|
+--f7 <= keyboard(65);
|
|
+--f8 <= keyboard(66);
|
|
+--f9 <= keyboard(67);
|
|
+--f10 <= keyboard(68);
|
|
+
|
|
+virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
|
|
+SYSTEM_RESET_REQUEST <= keyboard(63);
|
|
+
|
|
+process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
|
|
+ begin
|
|
+ keyboard_response <= (others=>'1');
|
|
+
|
|
+ if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
|
|
+ keyboard_response(0) <= '0';
|
|
+ end if;
|
|
+
|
|
+-- if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
|
|
+-- keyboard_response(0) <= '0';
|
|
+-- end if;
|
|
+
|
|
+ if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
|
|
+ keyboard_response(1) <= '0';
|
|
+ end if;
|
|
+
|
|
+ if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
|
|
+ keyboard_response(1) <= '0';
|
|
+ end if;
|
|
|
|
+ if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
|
|
+ keyboard_response(1) <= '0';
|
|
+ end if;
|
|
+end process;
|
|
+
|
|
+ -- decode address
|
|
+--decode_addr1 : complete_address_decoder
|
|
+-- generic map(width=>6)
|
|
+-- port map (addr_in=>keyboard_scan, addr_decoded=>keyboard_scan_decoded);
|
|
+
|
|
b2v_a_6502 : cpu
|
|
PORT MAP(CLK => CLK,
|
|
RESET => CPU_6502_RESET,
|
|
@@ -804,6 +1268,8 @@
|
|
CHANNEL_1 => SYNTHESIZED_WIRE_1,
|
|
CHANNEL_2 => SYNTHESIZED_WIRE_2,
|
|
CHANNEL_3 => SYNTHESIZED_WIRE_3,
|
|
+ COVOX_CHANNEL_0 => covox_channel0,
|
|
+ COVOX_CHANNEL_1 => covox_channel1,
|
|
CHANNEL_ENABLE => "1111",
|
|
VOLUME_OUT => AUDIO_LEFT);
|
|
|
|
@@ -848,6 +1314,7 @@
|
|
ZPU_DI => MEMORY_DATA,
|
|
ZPU_RAM_DI => ZPU_RAM_DATA,
|
|
ZPU_ROM_DI => ZPU_ROM_DATA,
|
|
+ ZPU_SECTOR_DI => zpu_sector_data,
|
|
MEMORY_FETCH => ZPU_FETCH,
|
|
ZPU_READ_ENABLE => ZPU_READ_ENABLE,
|
|
ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
|
|
@@ -867,6 +1334,8 @@
|
|
CHANNEL_1 => SYNTHESIZED_WIRE_5,
|
|
CHANNEL_2 => SYNTHESIZED_WIRE_6,
|
|
CHANNEL_3 => SYNTHESIZED_WIRE_7,
|
|
+ COVOX_CHANNEL_0 => covox_channel2,
|
|
+ COVOX_CHANNEL_1 => covox_channel3,
|
|
CHANNEL_ENABLE => "1111",
|
|
VOLUME_OUT => AUDIO_RIGHT);
|
|
|
|
@@ -944,24 +1413,26 @@
|
|
SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
|
|
|
|
|
|
-b2v_inst18 : pokey_ps2_decoder
|
|
-PORT MAP(CLK => CLK,
|
|
- RESET_N => RESET_N,
|
|
- KEY_EVENT => SYNTHESIZED_WIRE_8,
|
|
- KEY_EXTENDED => SYNTHESIZED_WIRE_9,
|
|
- KEY_UP => SYNTHESIZED_WIRE_10,
|
|
- KEY_CODE => SYNTHESIZED_WIRE_11,
|
|
- KEY_HELD => KEY_HELD,
|
|
- SHIFT_PRESSED => SHIFT_PRESSED,
|
|
- BREAK_PRESSED => BREAK_PRESSED,
|
|
- CONSOL_START => CONSOL_START,
|
|
- CONSOL_SELECT => CONSOL_SELECT,
|
|
- CONSOL_OPTION => CONSOL_OPTION,
|
|
- SYSTEM_RESET => SYSTEM_RESET_REQUEST,
|
|
- KBCODE => KBCODE,
|
|
- VIRTUAL_STICKS => VIRTUAL_STICKS,
|
|
- VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
|
|
- VIRTUAL_KEYS => VIRTUAL_KEYS);
|
|
+virtual_sticks <= (others=>'1');
|
|
+virtual_triggers <= "0011";
|
|
+--b2v_inst18 : pokey_ps2_decoder
|
|
+--PORT MAP(CLK => CLK,
|
|
+-- RESET_N => RESET_N,
|
|
+-- KEY_EVENT => SYNTHESIZED_WIRE_8,
|
|
+-- KEY_EXTENDED => SYNTHESIZED_WIRE_9,
|
|
+-- KEY_UP => SYNTHESIZED_WIRE_10,
|
|
+-- KEY_CODE => SYNTHESIZED_WIRE_11,
|
|
+-- KEY_HELD => KEY_HELD,
|
|
+-- SHIFT_PRESSED => SHIFT_PRESSED_DUMMY,
|
|
+-- BREAK_PRESSED => BREAK_PRESSED_DUMMY,
|
|
+-- CONSOL_START => CONSOL_START_DUMMY,
|
|
+-- CONSOL_SELECT => CONSOL_SELECT_DUMMY,
|
|
+-- CONSOL_OPTION => CONSOL_OPTION_DUMMY,
|
|
+-- SYSTEM_RESET => SYSTEM_RESET_REQUEST,
|
|
+-- KBCODE => KBCODE_dummy,
|
|
+-- VIRTUAL_STICKS => VIRTUAL_STICKS,
|
|
+-- VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
|
|
+-- VIRTUAL_KEYS => VIRTUAL_KEYS);
|
|
|
|
-- no cart!
|
|
CART_RD4 <= '0';
|
|
@@ -1003,9 +1474,9 @@
|
|
CACHE_POKEY_DATA => CACHE_POKEY_DO,
|
|
PORTB => PORTB_OUT,
|
|
RAM_DATA => RAM_DO,
|
|
- ram_select => RAM_SELECT,
|
|
+ ram_select => RAM_SELECT(2 downto 0),
|
|
ROM_DATA => ROM_DO,
|
|
- rom_select => ROM_SELECT,
|
|
+ rom_select => "00"&ROM_SELECT, -- TODO
|
|
SDRAM_DATA => SDRAM_DO,
|
|
ZPU_ADDR => ZPU_ADDR_FETCH,
|
|
ZPU_WRITE_DATA => ZPU_DO,
|
|
@@ -1038,7 +1509,10 @@
|
|
RAM_ADDR => RAM_ADDR,
|
|
ROM_ADDR => ROM_ADDR,
|
|
SDRAM_ADDR => SDRAM_ADDR,
|
|
- WRITE_DATA => WRITE_DATA);
|
|
+ WRITE_DATA => WRITE_DATA,
|
|
+ d6_wr_enable => covox_write_enable,
|
|
+ cart_select => "0000000",
|
|
+ cart_activate => '0');
|
|
|
|
b2v_inst21 : zpu_rom
|
|
PORT MAP(clock => CLK,
|
|
@@ -1058,10 +1532,9 @@
|
|
colour_in => SYNTHESIZED_WIRE_14,
|
|
VSYNC => VGA_VS,
|
|
HSYNC => VGA_HS,
|
|
- B => VGA_B,
|
|
- G => VGA_G,
|
|
- R => VGA_R);
|
|
-
|
|
+ B => VGA_B(5 downto 2),
|
|
+ G => VGA_G(5 downto 2),
|
|
+ R => VGA_R(5 downto 2));
|
|
|
|
b2v_inst23 : zpu_ram
|
|
PORT MAP(wren => ZPU_STACK_WRITE(2),
|
|
@@ -1105,7 +1578,11 @@
|
|
RAM_SELECT => RAM_SELECT,
|
|
ROM_SELECT => ROM_SELECT,
|
|
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
|
|
- ZPU_HEX => ZPU_HEX);
|
|
+ ZPU_HEX => ZPU_HEX,
|
|
+ sector_request => mist_sector_request,
|
|
+ sector => mist_sector,
|
|
+ sector_ready => mist_sector_ready_sync
|
|
+ );
|
|
|
|
|
|
b2v_inst25 : zpu_ram
|
|
@@ -1133,7 +1610,7 @@
|
|
|
|
|
|
b2v_inst5 : pll
|
|
-PORT MAP(inclk0 => FPGA_CLK,
|
|
+PORT MAP(inclk0 => CLOCK_27(0),
|
|
c0 => CLK_SDRAM,
|
|
c1 => CLK,
|
|
c2 => SDRAM_CLK,
|
|
@@ -1164,27 +1641,27 @@
|
|
DATA_OUT => POKEY_DO,
|
|
keyboard_scan => KEYBOARD_SCAN);
|
|
|
|
- process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
|
|
- begin
|
|
- keyboard_response <= (others=>'1');
|
|
-
|
|
- if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
|
|
- keyboard_response(0) <= '0';
|
|
- end if;
|
|
-
|
|
- if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
|
|
- keyboard_response(1) <= '0';
|
|
- end if;
|
|
-
|
|
- if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
|
|
- keyboard_response(1) <= '0';
|
|
- end if;
|
|
-
|
|
- if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
|
|
- keyboard_response(1) <= '0';
|
|
- end if;
|
|
- end process;
|
|
-
|
|
+-- process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
|
|
+-- begin
|
|
+-- keyboard_response <= (others=>'1');
|
|
+--
|
|
+-- if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
|
|
+-- keyboard_response(0) <= '0';
|
|
+-- end if;
|
|
+--
|
|
+-- if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
|
|
+-- keyboard_response(1) <= '0';
|
|
+-- end if;
|
|
+--
|
|
+-- if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
|
|
+-- keyboard_response(1) <= '0';
|
|
+-- end if;
|
|
+--
|
|
+-- if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
|
|
+-- keyboard_response(1) <= '0';
|
|
+-- end if;
|
|
+-- end process;
|
|
+--
|
|
b2v_inst8 : gtia
|
|
PORT MAP(CLK => CLK,
|
|
WR_EN => GTIA_WRITE_ENABLE,
|
|
@@ -1281,39 +1758,7 @@
|
|
RAM_DATA => ram_do(7 downto 0)
|
|
);
|
|
|
|
---b2v_inst20 : sdram_statemachine
|
|
---GENERIC MAP(ADDRESS_WIDTH => 22,
|
|
--- AP_BIT => 10,
|
|
--- COLUMN_WIDTH => 8,
|
|
--- ROW_WIDTH => 12
|
|
--- )
|
|
---PORT MAP(CLK_SYSTEM => CLK,
|
|
--- CLK_SDRAM => CLK_SDRAM,
|
|
--- RESET_N => RESET_N,
|
|
--- READ_EN => SDRAM_READ_ENABLE,
|
|
--- WRITE_EN => SDRAM_WRITE_ENABLE,
|
|
--- REQUEST => SDRAM_REQUEST,
|
|
--- BYTE_ACCESS => WIDTH_8BIT_ACCESS,
|
|
--- WORD_ACCESS => WIDTH_16BIT_ACCESS,
|
|
--- LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
|
|
--- REFRESH => SDRAM_REFRESH,
|
|
--- ADDRESS_IN => SDRAM_ADDR,
|
|
--- DATA_IN => WRITE_DATA,
|
|
--- SDRAM_DQ => SDRAM_DQ,
|
|
--- REPLY => SDRAM_REPLY,
|
|
--- SDRAM_BA0 => SDRAM_BA(0),
|
|
--- SDRAM_BA1 => SDRAM_BA(1),
|
|
--- SDRAM_CKE => SDRAM_A(12),
|
|
--- SDRAM_CS_N => SDRAM_CS_N,
|
|
--- SDRAM_RAS_N => SDRAM_RAS_N,
|
|
--- SDRAM_CAS_N => SDRAM_CAS_N,
|
|
--- SDRAM_WE_N => SDRAM_WE_N,
|
|
--- SDRAM_ldqm => SDRAM_DQM_n(0),
|
|
--- SDRAM_udqm => SDRAM_DQM_n(1),
|
|
--- DATA_OUT => SDRAM_DO,
|
|
--- SDRAM_ADDR => SDRAM_A(11 downto 0));
|
|
-
|
|
-b2v_inst20 : sdram_statemachine_mcc
|
|
+b2v_inst20 : sdram_statemachine
|
|
GENERIC MAP(ADDRESS_WIDTH => 22,
|
|
AP_BIT => 10,
|
|
COLUMN_WIDTH => 8,
|
|
@@ -1332,18 +1777,70 @@
|
|
ADDRESS_IN => SDRAM_ADDR,
|
|
DATA_IN => WRITE_DATA,
|
|
SDRAM_DQ => SDRAM_DQ,
|
|
- REPLY => SDRAM_REQUEST_COMPLETE,
|
|
+ COMPLETE => SDRAM_REQUEST_COMPLETE,
|
|
SDRAM_BA0 => SDRAM_BA(0),
|
|
SDRAM_BA1 => SDRAM_BA(1),
|
|
- --SDRAM_CKE => SDRAM_A(12), -- TODO?
|
|
- SDRAM_CS_N => SDRAM_CS_N,
|
|
- SDRAM_RAS_N => SDRAM_RAS_N,
|
|
- SDRAM_CAS_N => SDRAM_CAS_N,
|
|
- SDRAM_WE_N => SDRAM_WE_N,
|
|
- SDRAM_ldqm => SDRAM_DQM_n(0),
|
|
- SDRAM_udqm => SDRAM_DQM_n(1),
|
|
+ SDRAM_CKE => SDRAM_CKE,
|
|
+ SDRAM_CS_N => SDRAM_nCS,
|
|
+ SDRAM_RAS_N => SDRAM_nRAS,
|
|
+ SDRAM_CAS_N => SDRAM_nCAS,
|
|
+ SDRAM_WE_N => SDRAM_nWE,
|
|
+ SDRAM_ldqm => SDRAM_DQML,
|
|
+ SDRAM_udqm => SDRAM_DQMH,
|
|
DATA_OUT => SDRAM_DO,
|
|
- SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
|
|
+ SDRAM_ADDR => SDRAM_A(11 downto 0));
|
|
+
|
|
+SDRAM_A(12) <= '0';
|
|
+
|
|
+--b2v_inst20 : sdram_statemachine_mcc
|
|
+--GENERIC MAP(ADDRESS_WIDTH => 22,
|
|
+-- AP_BIT => 10,
|
|
+-- COLUMN_WIDTH => 8,
|
|
+-- ROW_WIDTH => 12
|
|
+-- )
|
|
+--PORT MAP(CLK_SYSTEM => CLK,
|
|
+-- CLK_SDRAM => CLK_SDRAM,
|
|
+-- RESET_N => RESET_N,
|
|
+-- READ_EN => SDRAM_READ_ENABLE,
|
|
+-- WRITE_EN => SDRAM_WRITE_ENABLE,
|
|
+-- REQUEST => SDRAM_REQUEST,
|
|
+-- BYTE_ACCESS => WIDTH_8BIT_ACCESS,
|
|
+-- WORD_ACCESS => WIDTH_16BIT_ACCESS,
|
|
+-- LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
|
|
+-- REFRESH => SDRAM_REFRESH,
|
|
+-- ADDRESS_IN => SDRAM_ADDR,
|
|
+-- DATA_IN => WRITE_DATA,
|
|
+-- SDRAM_DQ => SDRAM_DQ,
|
|
+-- REPLY => SDRAM_REQUEST_COMPLETE,
|
|
+-- SDRAM_BA0 => SDRAM_BA(0),
|
|
+-- SDRAM_BA1 => SDRAM_BA(1),
|
|
+-- --SDRAM_CKE => SDRAM_A(12), -- TODO?
|
|
+-- SDRAM_CS_N => SDRAM_nCS,
|
|
+-- SDRAM_RAS_N => SDRAM_nRAS,
|
|
+-- SDRAM_CAS_N => SDRAM_nCAS,
|
|
+-- SDRAM_WE_N => SDRAM_nWE,
|
|
+-- SDRAM_ldqm => SDRAM_DQML,
|
|
+-- SDRAM_udqm => SDRAM_DQMH,
|
|
+-- DATA_OUT => SDRAM_DO,
|
|
+-- SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
|
|
|
|
+--SDRAM_CKE <= '1';
|
|
+LED <= '0';
|
|
+VGA_R(1 downto 0) <= "00";
|
|
+VGA_G(1 downto 0) <= "00";
|
|
+VGA_B(1 downto 0) <= "00";
|
|
+
|
|
+covox1 : covox
|
|
+ PORT map
|
|
+ (
|
|
+ clk => clk,
|
|
+ addr => pbi_addr(1 downto 0),
|
|
+ data_in => WRITE_DATA(7 DOWNTO 0),
|
|
+ wr_en => covox_write_enable,
|
|
+ covox_channel0 => covox_channel0,
|
|
+ covox_channel1 => covox_channel1,
|
|
+ covox_channel2 => covox_channel2,
|
|
+ covox_channel3 => covox_channel3
|
|
+ );
|
|
|
|
END bdf_type;
|
|
\ No newline at end of file
|
|
Only in atari800core_v1_20140312_mist/: ataribas.mif
|
|
Only in atari800core_v1_20140312_mist/: basic.cmp
|
|
Only in atari800core_v1_20140312_mist/: basic.qip
|
|
Only in atari800core_v1_20140312_mist/: basic.vhd
|
|
Only in atari800core_v1_20140312_mist/: covox.vhd
|
|
Only in atari800core_v1_20140312_mist/: covox.vhd.bak
|
|
Only in atari800core_v1_20140312_mist/: custom_io.vhd
|
|
Only in atari800core_v1_20140312_mist/: data_io.v~
|
|
Only in atari800core_v1_20140312_mist/: data_io.vhdl
|
|
Only in atari800core_v1_20140312_mist/: data_io.vhdl.bak
|
|
Only in atari800core_v1_20140312_mist/: generic_ram_infer.vhdl
|
|
Only in atari800core_v1_20140312_mist/: generic_ram_infer.vhdl.bak
|
|
diff -ur atari800core_v1_20140121_mcc216/internalromram.vhd atari800core_v1_20140312_mist/internalromram.vhd
|
|
--- atari800core_v1_20140121_mcc216/internalromram.vhd 2014-01-21 20:44:04.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/internalromram.vhd 2014-03-08 17:35:06.000000000 +0000
|
|
@@ -34,16 +34,16 @@
|
|
);
|
|
END component;
|
|
|
|
-component romlo IS
|
|
+component rom16 IS
|
|
PORT
|
|
(
|
|
- address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
|
|
+ address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
|
|
clock : IN STD_LOGIC := '1';
|
|
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
|
|
);
|
|
END component;
|
|
|
|
-component romhi IS
|
|
+component basic IS
|
|
PORT
|
|
(
|
|
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
|
|
@@ -55,8 +55,8 @@
|
|
signal rom_request_reg : std_logic;
|
|
signal ram_request_reg : std_logic;
|
|
|
|
- signal ROMLO_DATA : std_logic_vector(7 downto 0);
|
|
- signal ROMHI_DATA : std_logic_vector(7 downto 0);
|
|
+ signal ROM16_DATA : std_logic_vector(7 downto 0);
|
|
+ signal BASIC_DATA : std_logic_vector(7 downto 0);
|
|
|
|
signal RAM_WR_ENABLE_REAL : std_logic;
|
|
signal IRAM_DATA : std_logic_vector(7 downto 0);
|
|
@@ -74,26 +74,42 @@
|
|
end process;
|
|
|
|
rom_request_complete <= rom_request_reg;
|
|
- ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;
|
|
- romlo1 : romlo
|
|
- PORT MAP(clock => clock,
|
|
- address => rom_addr(10 downto 0),
|
|
- q => ROMLO_data
|
|
- );
|
|
- romhi1 : romhi
|
|
- PORT MAP(clock => clock,
|
|
- address => rom_addr(12 downto 0),
|
|
- q => ROMHI_data
|
|
- );
|
|
-
|
|
- ramint1 : ramint
|
|
- PORT MAP(clock => clock,
|
|
- address => ram_addr(12 downto 0),
|
|
- data => ram_data_in(7 downto 0),
|
|
- wren => RAM_WR_ENABLE_REAL,
|
|
- q => iram_data
|
|
- );
|
|
+ --C000 = basic.
|
|
+ --0000-07FF = low
|
|
+ --0800-27ff high
|
|
+
|
|
+ process(rom16_data,basic_data, rom_addr(15 downto 0))
|
|
+ begin
|
|
+ ROM_DATA <= ROM16_DATA;
|
|
+ if (rom_addr(15)='1') then
|
|
+ ROM_DATA <= BASIC_DATA;
|
|
+ end if;
|
|
+ end process;
|
|
+
|
|
+
|
|
+ --ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;
|
|
+ --ROM_DATA <= ROMHI_DATA;
|
|
+-- basic1 : basic
|
|
+-- PORT MAP(clock => clock,
|
|
+-- address => rom_addr(12 downto 0),
|
|
+-- q => BASIC_data
|
|
+-- );
|
|
+--
|
|
+-- rom16a : rom16
|
|
+-- PORT MAP(clock => clock,
|
|
+-- address => rom_addr(13 downto 0),
|
|
+-- q => ROM16_data
|
|
+-- );
|
|
+--
|
|
+-- ramint1 : ramint
|
|
+-- PORT MAP(clock => clock,
|
|
+-- address => ram_addr(12 downto 0),
|
|
+-- data => ram_data_in(7 downto 0),
|
|
+-- wren => RAM_WR_ENABLE_REAL,
|
|
+-- q => iram_data
|
|
+-- );
|
|
ram_request_complete <= ram_request_reg;
|
|
+
|
|
RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
|
|
RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
|
|
end vhdl;
|
|
\ No newline at end of file
|
|
Only in atari800core_v1_20140312_mist/: mist_sector_buffer.cmp
|
|
Only in atari800core_v1_20140312_mist/: mist_sector_buffer.qip
|
|
Only in atari800core_v1_20140312_mist/: mist_sector_buffer.vhd
|
|
Only in atari800core_v1_20140312_mist/: os16.mif
|
|
Only in atari800core_v1_20140312_mist/: output_file.rbf
|
|
diff -ur atari800core_v1_20140121_mcc216/pll.bsf atari800core_v1_20140312_mist/pll.bsf
|
|
--- atari800core_v1_20140121_mcc216/pll.bsf 2014-01-26 09:19:13.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/pll.bsf 2014-03-01 09:10:29.000000000 +0000
|
|
@@ -20,8 +20,8 @@
|
|
*/
|
|
(header "symbol" (version "1.2"))
|
|
(symbol
|
|
- (rect 0 0 248 184)
|
|
- (text "pll" (rect 118 0 133 16)(font "Arial" (font_size 10)))
|
|
+ (rect 0 0 256 184)
|
|
+ (text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
|
|
(text "inst" (rect 8 168 25 180)(font "Arial" ))
|
|
(port
|
|
(pt 0 64)
|
|
@@ -31,70 +31,70 @@
|
|
(line (pt 0 64)(pt 40 64))
|
|
)
|
|
(port
|
|
- (pt 248 64)
|
|
+ (pt 256 64)
|
|
(output)
|
|
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
|
|
- (text "c0" (rect 232 50 242 63)(font "Arial" (font_size 8)))
|
|
+ (text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8)))
|
|
)
|
|
(port
|
|
- (pt 248 80)
|
|
+ (pt 256 80)
|
|
(output)
|
|
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
|
|
- (text "c1" (rect 232 66 240 79)(font "Arial" (font_size 8)))
|
|
+ (text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8)))
|
|
)
|
|
(port
|
|
- (pt 248 96)
|
|
+ (pt 256 96)
|
|
(output)
|
|
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
|
|
- (text "c2" (rect 232 82 242 95)(font "Arial" (font_size 8)))
|
|
+ (text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8)))
|
|
)
|
|
(port
|
|
- (pt 248 112)
|
|
+ (pt 256 112)
|
|
(output)
|
|
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
|
|
- (text "locked" (rect 213 98 242 111)(font "Arial" (font_size 8)))
|
|
+ (text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8)))
|
|
)
|
|
(drawing
|
|
- (text "Cyclone III" (rect 186 168 417 347)(font "Arial" ))
|
|
- (text "inclk0 frequency: 5.000 MHz" (rect 50 59 218 129)(font "Arial" ))
|
|
+ (text "Cyclone III" (rect 194 168 433 347)(font "Arial" ))
|
|
+ (text "inclk0 frequency: 27.000 MHz" (rect 50 59 223 129)(font "Arial" ))
|
|
(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
|
|
(text "Clk " (rect 51 93 116 197)(font "Arial" ))
|
|
(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
|
|
- (text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
|
|
- (text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
|
|
+ (text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
|
|
+ (text "DC (%)" (rect 133 93 296 197)(font "Arial" ))
|
|
(text "c0" (rect 54 107 116 225)(font "Arial" ))
|
|
- (text "23/2" (rect 74 107 164 225)(font "Arial" ))
|
|
- (text "0.00" (rect 104 107 224 225)(font "Arial" ))
|
|
- (text "50.00" (rect 136 107 293 225)(font "Arial" ))
|
|
+ (text "69/16" (rect 72 107 165 225)(font "Arial" ))
|
|
+ (text "0.00" (rect 105 107 226 225)(font "Arial" ))
|
|
+ (text "50.00" (rect 137 107 295 225)(font "Arial" ))
|
|
(text "c1" (rect 54 121 115 253)(font "Arial" ))
|
|
- (text "23/2" (rect 74 121 164 253)(font "Arial" ))
|
|
- (text "0.00" (rect 104 121 224 253)(font "Arial" ))
|
|
- (text "50.00" (rect 136 121 293 253)(font "Arial" ))
|
|
+ (text "69/32" (rect 72 121 165 253)(font "Arial" ))
|
|
+ (text "0.00" (rect 105 121 226 253)(font "Arial" ))
|
|
+ (text "50.00" (rect 137 121 295 253)(font "Arial" ))
|
|
(text "c2" (rect 54 135 116 281)(font "Arial" ))
|
|
- (text "23/2" (rect 74 135 164 281)(font "Arial" ))
|
|
- (text "0.00" (rect 104 135 224 281)(font "Arial" ))
|
|
- (text "50.00" (rect 136 135 293 281)(font "Arial" ))
|
|
- (line (pt 0 0)(pt 249 0))
|
|
- (line (pt 249 0)(pt 249 185))
|
|
- (line (pt 0 185)(pt 249 185))
|
|
+ (text "69/16" (rect 72 135 165 281)(font "Arial" ))
|
|
+ (text "-67.06" (rect 101 135 226 281)(font "Arial" ))
|
|
+ (text "50.00" (rect 137 135 295 281)(font "Arial" ))
|
|
+ (line (pt 0 0)(pt 257 0))
|
|
+ (line (pt 257 0)(pt 257 185))
|
|
+ (line (pt 0 185)(pt 257 185))
|
|
(line (pt 0 0)(pt 0 185))
|
|
- (line (pt 48 91)(pt 164 91))
|
|
- (line (pt 48 104)(pt 164 104))
|
|
- (line (pt 48 118)(pt 164 118))
|
|
- (line (pt 48 132)(pt 164 132))
|
|
- (line (pt 48 146)(pt 164 146))
|
|
+ (line (pt 48 91)(pt 165 91))
|
|
+ (line (pt 48 104)(pt 165 104))
|
|
+ (line (pt 48 118)(pt 165 118))
|
|
+ (line (pt 48 132)(pt 165 132))
|
|
+ (line (pt 48 146)(pt 165 146))
|
|
(line (pt 48 91)(pt 48 146))
|
|
(line (pt 69 91)(pt 69 146)(line_width 3))
|
|
- (line (pt 95 91)(pt 95 146)(line_width 3))
|
|
- (line (pt 129 91)(pt 129 146)(line_width 3))
|
|
- (line (pt 163 91)(pt 163 146))
|
|
- (line (pt 40 48)(pt 199 48))
|
|
- (line (pt 199 48)(pt 199 167))
|
|
- (line (pt 40 167)(pt 199 167))
|
|
+ (line (pt 96 91)(pt 96 146)(line_width 3))
|
|
+ (line (pt 130 91)(pt 130 146)(line_width 3))
|
|
+ (line (pt 164 91)(pt 164 146))
|
|
+ (line (pt 40 48)(pt 207 48))
|
|
+ (line (pt 207 48)(pt 207 167))
|
|
+ (line (pt 40 167)(pt 207 167))
|
|
(line (pt 40 48)(pt 40 167))
|
|
- (line (pt 247 64)(pt 199 64))
|
|
- (line (pt 247 80)(pt 199 80))
|
|
- (line (pt 247 96)(pt 199 96))
|
|
- (line (pt 247 112)(pt 199 112))
|
|
+ (line (pt 255 64)(pt 207 64))
|
|
+ (line (pt 255 80)(pt 207 80))
|
|
+ (line (pt 255 96)(pt 207 96))
|
|
+ (line (pt 255 112)(pt 207 112))
|
|
)
|
|
)
|
|
diff -ur atari800core_v1_20140121_mcc216/PLLJ_PLLSPE_INFO.txt atari800core_v1_20140312_mist/PLLJ_PLLSPE_INFO.txt
|
|
--- atari800core_v1_20140121_mcc216/PLLJ_PLLSPE_INFO.txt 2014-02-03 19:43:41.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/PLLJ_PLLSPE_INFO.txt 2014-03-12 05:05:11.000000000 +0000
|
|
@@ -1,5 +1,5 @@
|
|
PLL_Name pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
|
|
-PLLJITTER NA
|
|
+PLLJITTER 26
|
|
PLLSPEmax 84
|
|
PLLSPEmin -53
|
|
|
|
diff -ur atari800core_v1_20140121_mcc216/pll.vhd atari800core_v1_20140312_mist/pll.vhd
|
|
--- atari800core_v1_20140121_mcc216/pll.vhd 2014-01-26 09:19:13.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/pll.vhd 2014-03-01 09:10:29.000000000 +0000
|
|
@@ -154,20 +154,20 @@
|
|
altpll_component : altpll
|
|
GENERIC MAP (
|
|
bandwidth_type => "AUTO",
|
|
- clk0_divide_by => 2,
|
|
+ clk0_divide_by => 16,
|
|
clk0_duty_cycle => 50,
|
|
- clk0_multiply_by => 23,
|
|
+ clk0_multiply_by => 69,
|
|
clk0_phase_shift => "0",
|
|
- clk1_divide_by => 2,
|
|
+ clk1_divide_by => 32,
|
|
clk1_duty_cycle => 50,
|
|
- clk1_multiply_by => 23,
|
|
+ clk1_multiply_by => 69,
|
|
clk1_phase_shift => "0",
|
|
- clk2_divide_by => 2,
|
|
+ clk2_divide_by => 16,
|
|
clk2_duty_cycle => 50,
|
|
- clk2_multiply_by => 23,
|
|
- clk2_phase_shift => "0",
|
|
+ clk2_multiply_by => 69,
|
|
+ clk2_phase_shift => "-1600",
|
|
compensate_clock => "CLK0",
|
|
- inclk0_input_frequency => 200000,
|
|
+ inclk0_input_frequency => 37037,
|
|
intended_device_family => "Cyclone III",
|
|
lpm_hint => "CBX_MODULE_PREFIX=pll",
|
|
lpm_type => "altpll",
|
|
@@ -246,15 +246,15 @@
|
|
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
|
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
|
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
|
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
|
|
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
|
|
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
|
|
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
|
|
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
|
|
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
|
|
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
|
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
|
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
|
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000"
|
|
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
|
|
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000"
|
|
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
|
|
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
|
|
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
|
|
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
|
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
|
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
|
@@ -262,7 +262,7 @@
|
|
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
|
|
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
|
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
|
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
|
|
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
|
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
|
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
|
@@ -281,13 +281,13 @@
|
|
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
|
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
|
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
|
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
|
|
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
|
|
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
|
|
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
|
|
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
|
|
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
|
|
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
|
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
|
|
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
|
|
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
|
|
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
|
|
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
|
|
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
|
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
|
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
|
@@ -298,7 +298,7 @@
|
|
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
|
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
|
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
|
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
|
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.60000000"
|
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
|
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
|
|
@@ -340,20 +340,20 @@
|
|
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
|
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
|
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
|
|
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
|
|
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
|
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
|
|
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
|
|
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
|
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
|
|
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
|
|
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
|
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
|
|
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
|
|
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
|
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
|
|
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
|
|
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
|
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
|
|
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
|
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
|
|
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1600"
|
|
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
|
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
|
|
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
|
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
|
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
|
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
|
diff -ur atari800core_v1_20140121_mcc216/pokey_mixer.vhdl atari800core_v1_20140312_mist/pokey_mixer.vhdl
|
|
--- atari800core_v1_20140121_mcc216/pokey_mixer.vhdl 2014-01-17 20:20:16.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/pokey_mixer.vhdl 2014-03-09 17:25:18.000000000 +0000
|
|
@@ -22,6 +22,9 @@
|
|
CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
|
|
|
|
GTIA_SOUND : IN STD_LOGIC;
|
|
+
|
|
+ COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
|
|
+ COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
|
|
|
|
VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
|
|
);
|
|
@@ -30,6 +33,7 @@
|
|
ARCHITECTURE vhdl OF pokey_mixer IS
|
|
signal volume_reg : std_logic_vector(15 downto 0);
|
|
signal volume_next : std_logic_vector(15 downto 0);
|
|
+ signal volume_next_real : std_logic_vector(15 downto 0);
|
|
|
|
signal volume_sum : std_logic_vector(5 downto 0);
|
|
|
|
@@ -38,13 +42,13 @@
|
|
signal channel_2_en : std_logic_vector(3 downto 0);
|
|
signal channel_3_en : std_logic_vector(3 downto 0);
|
|
|
|
- signal gtia_en : std_logic_vector(5 downto 0);
|
|
+ signal gtia_en : std_logic_vector(15 downto 0);
|
|
BEGIN
|
|
-- register
|
|
process(clk)
|
|
begin
|
|
if (clk'event and clk='1') then
|
|
- volume_reg <= volume_next;
|
|
+ volume_reg <= volume_next_real;
|
|
end if;
|
|
end process;
|
|
|
|
@@ -73,9 +77,7 @@
|
|
-- end if;
|
|
end process;
|
|
|
|
- gtia_en <= "0000">ia_sound>ia_sound; -- only room for 3 more! TODO, regenerate...
|
|
-
|
|
- process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
|
|
+ process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_en)
|
|
begin
|
|
volume_sum <=
|
|
std_logic_vector
|
|
@@ -89,12 +91,13 @@
|
|
unsigned('0'&CHANNEL_2_en) +
|
|
unsigned('0'&CHANNEL_3_en)
|
|
))
|
|
- +
|
|
- unsigned(gtia_en)
|
|
);
|
|
end process;
|
|
|
|
- process (volume_sum)
|
|
+ gtia_en(15 downto 13) <= (others=>'0');
|
|
+ gtia_en(12) <= gtia_sound;
|
|
+ gtia_en(11 downto 0) <= (others=>'0');
|
|
+ process (volume_sum, volume_next, gtia_en, covOX_CHANNEL_0,covOX_CHANNEL_1)
|
|
begin
|
|
case volume_sum is
|
|
when "000000" =>
|
|
@@ -223,9 +226,24 @@
|
|
volume_next <= X"79FF"; -- in case GTIA playing at full vol!
|
|
end case;
|
|
|
|
+-- volume_next_real <= std_LOGIC_vector(
|
|
+-- (unsigned('0'&volume_next(15 downto 1))
|
|
+-- + unsigned(gtia_en))
|
|
+-- + (unsigned("00"&covox_CHANNEL_0)
|
|
+-- + unsigned("00"&covox_CHANNEL_1)));
|
|
+
|
|
+ --volume_next_real <= '0'&volume_next(15 downto 1);
|
|
+
|
|
+ volume_next_real <= std_LOGIC_vector(
|
|
+ (unsigned("00"&volume_next(15 downto 2))
|
|
+ + unsigned(gtia_en))
|
|
+ + (unsigned("000"&covox_CHANNEL_0&"00000")
|
|
+ + unsigned("000"&covox_CHANNEL_1&"00000")));
|
|
+
|
|
end process;
|
|
|
|
-- output
|
|
+ -- TODO
|
|
volume_out <= volume_reg;
|
|
|
|
END vhdl;
|
|
\ No newline at end of file
|
|
Only in atari800core_v1_20140312_mist/: pokey_mixer.vhdl.bak
|
|
Only in atari800core_v1_20140312_mist/: rom16.cmp
|
|
Only in atari800core_v1_20140312_mist/: rom16.qip
|
|
Only in atari800core_v1_20140312_mist/: rom16.vhd
|
|
diff -ur atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl atari800core_v1_20140312_mist/sdram_statemachine.vhdl
|
|
--- atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl 2014-01-22 21:37:54.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/sdram_statemachine.vhdl 2014-02-16 20:26:57.000000000 +0000
|
|
@@ -28,13 +28,13 @@
|
|
ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
|
|
READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
|
|
WRITE_EN : in std_logic;
|
|
- REQUEST : in std_logic; -- Toggle this to issue a new request
|
|
+ REQUEST : in std_logic; -- set true to request
|
|
BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
|
|
WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
|
|
LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
|
|
REFRESH : in std_logic;
|
|
|
|
- REPLY : out std_logic; -- This matches the request once complete
|
|
+ COMPLETE : out std_logic;
|
|
DATA_OUT : out std_logic_vector(31 downto 0);
|
|
|
|
-- sdram itself
|
|
@@ -184,6 +184,9 @@
|
|
signal udqm_reg : std_logic;
|
|
signal cke_reg : std_logic;
|
|
|
|
+ signal sdram_request_reg : std_logic;
|
|
+ signal sdram_request_next : std_logic;
|
|
+
|
|
BEGIN
|
|
-- register
|
|
process(CLK_SDRAM,reset_n)
|
|
@@ -247,6 +250,8 @@
|
|
|
|
data_out_sreg <= (others=>'0');
|
|
reply_sreg <= '0';
|
|
+
|
|
+ sdram_request_reg <= '0';
|
|
elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
|
|
data_in_sreg <= data_in_snext;
|
|
address_in_sreg <= address_in_snext;
|
|
@@ -258,11 +263,13 @@
|
|
|
|
data_out_sreg <= data_out_snext;
|
|
reply_sreg <= reply_snext;
|
|
+
|
|
+ sdram_request_reg <= sdram_request_next;
|
|
end if;
|
|
end process;
|
|
|
|
-- Inputs - NB, clocked at a smaller multiple
|
|
- process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, request, byte_access, word_access, longword_access, refresh)
|
|
+ process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, sdram_request_next, byte_access, word_access, longword_access, refresh)
|
|
begin
|
|
data_in_snext <= data_in_sreg;
|
|
address_in_snext <= address_in_sreg;
|
|
@@ -275,12 +282,12 @@
|
|
|
|
-- only snap inputs on new request
|
|
-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
|
|
- if ((request xor request_sreg) = '1') then
|
|
+ if ((sdram_request_next xor request_sreg) = '1') then
|
|
data_in_snext <= data_in;
|
|
address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
|
|
read_en_snext <= read_en;
|
|
write_en_snext <= write_en;
|
|
- request_snext <= request;
|
|
+ request_snext <= sdram_request_next;
|
|
|
|
dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
|
|
dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
|
|
@@ -509,7 +516,11 @@
|
|
data_out_snext <= data_out_reg;
|
|
|
|
-- outputs to rest of system
|
|
- REPLY <= reply_sreg;
|
|
+ --REPLY <= reply_sreg;
|
|
DATA_OUT <= DATA_OUT_sreg;
|
|
-
|
|
+
|
|
+ -- a little sdram glue - move to sdram wrapper?
|
|
+ COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
|
|
+ sdram_request_next <= sdram_request_reg xor request;
|
|
+
|
|
END vhdl;
|
|
Only in atari800core_v1_20140312_mist/: stp1.stp
|
|
Only in atari800core_v1_20140312_mist/: user_io.v
|
|
Only in atari800core_v1_20140312_mist/: user_io.v.bak
|
|
diff -ur atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif atari800core_v1_20140312_mist/zpu/HelloTinyROM_ROM.mif
|
|
--- atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif 2014-01-31 21:09:40.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/zpu/HelloTinyROM_ROM.mif 2014-03-09 18:12:34.000000000 +0000
|
|
@@ -169,8 +169,8 @@
|
|
009e : 00000000;
|
|
009f : 00000000;
|
|
00a0 : 71fc0608;
|
|
-00a1 : 0b0b80f5;
|
|
-00a2 : d0738306;
|
|
+00a1 : 0b0b80ef;
|
|
+00a2 : 98738306;
|
|
00a3 : 10100508;
|
|
00a4 : 060b0b0b;
|
|
00a5 : 88a20400;
|
|
@@ -216,7 +216,7 @@
|
|
00cd : 00000000;
|
|
00ce : 00000000;
|
|
00cf : 00000000;
|
|
-00d0 : 810b80fb;
|
|
+00d0 : 810b80f5;
|
|
00d1 : ac0c5104;
|
|
00d2 : 00000000;
|
|
00d3 : 00000000;
|
|
@@ -289,8 +289,8 @@
|
|
0116 : 83e08008;
|
|
0117 : 83e08408;
|
|
0118 : 83e08808;
|
|
-0119 : 757580ef;
|
|
-011a : fe2d5050;
|
|
+0119 : 757580e9;
|
|
+011a : c62d5050;
|
|
011b : 83e08008;
|
|
011c : 5683e088;
|
|
011d : 0c83e084;
|
|
@@ -299,7 +299,7 @@
|
|
0120 : e0800883;
|
|
0121 : e0840883;
|
|
0122 : e0880875;
|
|
-0123 : 7580ee92;
|
|
+0123 : 7580e7da;
|
|
0124 : 2d505083;
|
|
0125 : e0800856;
|
|
0126 : 83e0880c;
|
|
@@ -308,31 +308,31 @@
|
|
0129 : 51040000;
|
|
012a : 800489aa;
|
|
012b : 0489aa0b;
|
|
-012c : 80c1a404;
|
|
+012c : 80c1eb04;
|
|
012d : fd3d0d75;
|
|
012e : b9297681;
|
|
-012f : 2a0580fd;
|
|
-0130 : fc085473;
|
|
+012f : 2a0580f8;
|
|
+0130 : 80085473;
|
|
0131 : 0c853d0d;
|
|
0132 : 04803d0d;
|
|
0133 : 81ff5180;
|
|
-0134 : 0b83e0c8;
|
|
+0134 : 0b83e0cc;
|
|
0135 : 1234ff11;
|
|
0136 : 5170f438;
|
|
0137 : 823d0d04;
|
|
0138 : fa3d0d78;
|
|
-0139 : 0b0b80f6;
|
|
-013a : a85383e2;
|
|
-013b : f4525680;
|
|
-013c : cdd13f80;
|
|
+0139 : 0b0b80ef;
|
|
+013a : ec5383e2;
|
|
+013b : f8525680;
|
|
+013c : ce9b3f80;
|
|
013d : 5383e080;
|
|
013e : 08732e8a;
|
|
013f : 387283e0;
|
|
0140 : 800c883d;
|
|
0141 : 0d0483e0;
|
|
0142 : 945283e2;
|
|
-0143 : f45180ce;
|
|
-0144 : c53f83e0;
|
|
+0143 : f85180cf;
|
|
+0144 : 8f3f83e0;
|
|
0145 : 800880d5;
|
|
0146 : 3883e09d;
|
|
0147 : 33537280;
|
|
@@ -360,3685 +360,3494 @@
|
|
015d : 3d0d0483;
|
|
015e : e0940883;
|
|
015f : e0800c88;
|
|
-0160 : 3d0d04fd;
|
|
-0161 : 3d0d800b;
|
|
-0162 : 80fdec08;
|
|
-0163 : 5353ff72;
|
|
-0164 : 0c80fdf0;
|
|
-0165 : 0873710c;
|
|
-0166 : 5284d851;
|
|
-0167 : fe963f88;
|
|
-0168 : 800a5380;
|
|
-0169 : 73708105;
|
|
-016a : 553472a8;
|
|
-016b : 800a2e09;
|
|
-016c : 8106f038;
|
|
-016d : 80fdec08;
|
|
-016e : 5485aad5;
|
|
-016f : aad5740c;
|
|
-0170 : 80fdf008;
|
|
-0171 : 5285aad5;
|
|
-0172 : aad5720c;
|
|
-0173 : 82800a53;
|
|
-0174 : 80737084;
|
|
-0175 : 05550c72;
|
|
-0176 : 81800a2e;
|
|
-0177 : 098106f0;
|
|
-0178 : 3880740c;
|
|
-0179 : ff720c84;
|
|
-017a : d851fdc8;
|
|
-017b : 3f853d0d;
|
|
-017c : 04fd3d0d;
|
|
-017d : 800b80fd;
|
|
-017e : ec085353;
|
|
-017f : ff87c3e1;
|
|
-0180 : f0720c80;
|
|
-0181 : fdf00873;
|
|
-0182 : 710c528c;
|
|
-0183 : 9ac051fd;
|
|
-0184 : a33f8880;
|
|
-0185 : 0a538073;
|
|
-0186 : 70810555;
|
|
-0187 : 34728184;
|
|
-0188 : 80802e09;
|
|
-0189 : 8106ef38;
|
|
-018a : 80fdec08;
|
|
-018b : 5485aad5;
|
|
-018c : aad5740c;
|
|
-018d : 80fdf008;
|
|
-018e : 5285aad5;
|
|
-018f : aad5720c;
|
|
-0190 : 82800a53;
|
|
-0191 : 80737084;
|
|
-0192 : 05550c72;
|
|
-0193 : 84848080;
|
|
-0194 : 2e098106;
|
|
-0195 : ef388074;
|
|
-0196 : 0cff87c3;
|
|
-0197 : e1f0720c;
|
|
-0198 : 8c9ac051;
|
|
-0199 : fcce3f85;
|
|
-019a : 3d0d04ff;
|
|
-019b : 3d0d80fe;
|
|
-019c : 80087008;
|
|
-019d : 52527381;
|
|
-019e : 2e8b3870;
|
|
-019f : 81800772;
|
|
-01a0 : 0c833d0d;
|
|
-01a1 : 0470feff;
|
|
-01a2 : 06720c83;
|
|
-01a3 : 3d0d04ff;
|
|
-01a4 : 3d0d80fe;
|
|
-01a5 : 80087008;
|
|
-01a6 : 5252738b;
|
|
-01a7 : 3870ffbf;
|
|
-01a8 : 06720c83;
|
|
-01a9 : 3d0d0470;
|
|
-01aa : 80c00772;
|
|
-01ab : 0c833d0d;
|
|
-01ac : 04ff0b83;
|
|
-01ad : e0b00c80;
|
|
-01ae : cee33f80;
|
|
-01af : d1e73f83;
|
|
-01b0 : e08008f3;
|
|
-01b1 : 3880d4ac;
|
|
-01b2 : 3f800b83;
|
|
-01b3 : e0800c04;
|
|
-01b4 : 803d0d70;
|
|
-01b5 : 83e0800c;
|
|
-01b6 : 823d0d04;
|
|
-01b7 : ff3d0d73;
|
|
-01b8 : 70335351;
|
|
-01b9 : 81113371;
|
|
-01ba : 34718112;
|
|
-01bb : 34833d0d;
|
|
-01bc : 04fb3d0d;
|
|
-01bd : 77028405;
|
|
-01be : a2052256;
|
|
-01bf : 56807071;
|
|
-01c0 : 55555271;
|
|
-01c1 : 7527ac38;
|
|
-01c2 : 75137033;
|
|
-01c3 : 70147081;
|
|
-01c4 : ff065551;
|
|
-01c5 : 51517174;
|
|
-01c6 : 27893881;
|
|
-01c7 : 127081ff;
|
|
-01c8 : 06535171;
|
|
-01c9 : 81147083;
|
|
-01ca : ffff0655;
|
|
-01cb : 52547473;
|
|
-01cc : 26d63871;
|
|
-01cd : 83e0800c;
|
|
-01ce : 873d0d04;
|
|
-01cf : f83d0d7a;
|
|
-01d0 : 57800b8a;
|
|
-01d1 : 3d238070;
|
|
-01d2 : 7183e2e4;
|
|
-01d3 : 0c0b0b80;
|
|
-01d4 : f6ac5357;
|
|
-01d5 : 5880dabf;
|
|
-01d6 : 3f765180;
|
|
-01d7 : dab93f0b;
|
|
-01d8 : 0b80faf4;
|
|
-01d9 : 5180daaf;
|
|
-01da : 3f765180;
|
|
-01db : c2f13f83;
|
|
-01dc : e0800878;
|
|
-01dd : 2e8f380b;
|
|
-01de : 0b80f6b8;
|
|
-01df : 5180da97;
|
|
-01e0 : 3f8a3d0d;
|
|
-01e1 : 040b0b80;
|
|
-01e2 : f6c05180;
|
|
-01e3 : da893f75;
|
|
-01e4 : 17703355;
|
|
-01e5 : 5573802e;
|
|
-01e6 : 80fd3873;
|
|
-01e7 : ae2e8638;
|
|
-01e8 : 811656eb;
|
|
-01e9 : 39800b81;
|
|
-01ea : 16335556;
|
|
-01eb : 7380d82e;
|
|
-01ec : 09810683;
|
|
-01ed : 38815673;
|
|
-01ee : 80f83270;
|
|
-01ef : 30708025;
|
|
-01f0 : 78075151;
|
|
-01f1 : 5473802e;
|
|
-01f2 : 80cd3880;
|
|
-01f3 : 0b821633;
|
|
-01f4 : 55567380;
|
|
-01f5 : c62e0981;
|
|
-01f6 : 06833881;
|
|
-01f7 : 567380e6;
|
|
-01f8 : 32703070;
|
|
-01f9 : 80257807;
|
|
-01fa : 51515473;
|
|
-01fb : 802ea838;
|
|
-01fc : 800b8316;
|
|
-01fd : 33555673;
|
|
-01fe : 80c42e09;
|
|
-01ff : 81068338;
|
|
-0200 : 81567380;
|
|
-0201 : e4327030;
|
|
-0202 : 70802578;
|
|
-0203 : 07515154;
|
|
-0204 : 73802e83;
|
|
-0205 : 38815880;
|
|
-0206 : 0b8a3d23;
|
|
-0207 : 8a3dfc05;
|
|
-0208 : 53905283;
|
|
-0209 : e2e85180;
|
|
-020a : c2f53f89;
|
|
-020b : 3d225574;
|
|
-020c : 902e8e38;
|
|
-020d : 0b0b80f6;
|
|
-020e : c45180d8;
|
|
-020f : da3ffec1;
|
|
-0210 : 3983e2e8;
|
|
-0211 : 51fd953f;
|
|
-0212 : 83e2ea51;
|
|
-0213 : fd8e3f83;
|
|
-0214 : e2ec51fd;
|
|
-0215 : 873f800b;
|
|
-0216 : 83e3880c;
|
|
-0217 : 77812e81;
|
|
-0218 : 8c3883e2;
|
|
-0219 : e83383e2;
|
|
-021a : e9337188;
|
|
-021b : 2b075556;
|
|
-021c : 7383ffff;
|
|
-021d : 2e82ce38;
|
|
-021e : 7385962e;
|
|
-021f : 8e380b0b;
|
|
-0220 : 80f6dc51;
|
|
-0221 : 80d8903f;
|
|
-0222 : fdf7390b;
|
|
-0223 : 0b80f6f0;
|
|
-0224 : 5180d883;
|
|
-0225 : 3f7483e3;
|
|
-0226 : 900c83e2;
|
|
-0227 : ec3383e2;
|
|
-0228 : ed337188;
|
|
-0229 : 2b075555;
|
|
-022a : 7381802e;
|
|
-022b : 81d33873;
|
|
-022c : 82802e84;
|
|
-022d : 81387381;
|
|
-022e : ff2681b8;
|
|
-022f : 380b0b80;
|
|
-0230 : f6f85180;
|
|
-0231 : d7d13f83;
|
|
-0232 : e2ea3383;
|
|
-0233 : e2eb3371;
|
|
-0234 : 882b0752;
|
|
-0235 : 5680d8ce;
|
|
-0236 : 3f0b0b80;
|
|
-0237 : f6fc5180;
|
|
-0238 : d7b53f81;
|
|
-0239 : 0b83e2e4;
|
|
-023a : 0c8a3d0d;
|
|
-023b : 040b0b80;
|
|
-023c : f7805180;
|
|
-023d : d7a13f80;
|
|
-023e : 0b83e390;
|
|
-023f : 0c820b83;
|
|
-0240 : e2e834ff;
|
|
-0241 : 960b83e2;
|
|
-0242 : e9347651;
|
|
-0243 : f7d23f83;
|
|
-0244 : e0800854;
|
|
-0245 : 800b83e0;
|
|
-0246 : 800824a9;
|
|
-0247 : 3873842c;
|
|
-0248 : 7083ffff;
|
|
-0249 : 0670882a;
|
|
-024a : 57515474;
|
|
-024b : 83e2ea34;
|
|
-024c : 7383e2eb;
|
|
-024d : 34800b83;
|
|
-024e : e2ec34ff;
|
|
-024f : 800b83e2;
|
|
-0250 : ed34fed6;
|
|
-0251 : 3983e080;
|
|
-0252 : 088f0570;
|
|
-0253 : 842c7083;
|
|
-0254 : ffff0670;
|
|
-0255 : 882a5851;
|
|
-0256 : 51547483;
|
|
-0257 : e2ea3473;
|
|
-0258 : 83e2eb34;
|
|
-0259 : 800b83e2;
|
|
-025a : ec34ff80;
|
|
-025b : 0b83e2ed;
|
|
-025c : 34fea739;
|
|
-025d : 0b0b80f7;
|
|
-025e : 885180d6;
|
|
-025f : 9a3ffc81;
|
|
-0260 : 3983e2ea;
|
|
-0261 : 3383e2eb;
|
|
-0262 : 3371882b;
|
|
-0263 : 075558ad;
|
|
-0264 : 80742781;
|
|
-0265 : f2380b0b;
|
|
-0266 : 80f79851;
|
|
-0267 : 80d5f83f;
|
|
-0268 : 83e2ea33;
|
|
-0269 : 83e2eb33;
|
|
-026a : 71882b07;
|
|
-026b : 525680d6;
|
|
-026c : f53f0b0b;
|
|
-026d : 80f6fc51;
|
|
-026e : 80d5dc3f;
|
|
-026f : 810b83e2;
|
|
-0270 : e40cfea5;
|
|
-0271 : 390b0b80;
|
|
-0272 : f79c5180;
|
|
-0273 : d5c93ffe;
|
|
-0274 : 800b83e3;
|
|
-0275 : 900c810b;
|
|
-0276 : 83e3880c;
|
|
-0277 : ff0b83e2;
|
|
-0278 : e834ff0b;
|
|
-0279 : 83e2e934;
|
|
-027a : 7651f5f4;
|
|
-027b : 3f83e080;
|
|
-027c : 0883e394;
|
|
-027d : 0c83e080;
|
|
-027e : 0854800b;
|
|
-027f : 83e08008;
|
|
-0280 : 2480d338;
|
|
-0281 : 73842c70;
|
|
-0282 : 83ffff06;
|
|
-0283 : 70882a57;
|
|
-0284 : 51547483;
|
|
-0285 : e2ea3473;
|
|
-0286 : 83e2eb34;
|
|
-0287 : 800b83e2;
|
|
-0288 : ec34ff80;
|
|
-0289 : 0b83e2ed;
|
|
-028a : 34805574;
|
|
-028b : 17547333;
|
|
-028c : 83e2d816;
|
|
-028d : 34811555;
|
|
-028e : 748c2efc;
|
|
-028f : dd387417;
|
|
-0290 : 54733383;
|
|
-0291 : e2d81634;
|
|
-0292 : 81155574;
|
|
-0293 : 8c2e0981;
|
|
-0294 : 06d938fc;
|
|
-0295 : c53983e0;
|
|
-0296 : 80088f05;
|
|
-0297 : 70842c70;
|
|
-0298 : 83ffff06;
|
|
-0299 : 70882a58;
|
|
-029a : 51515474;
|
|
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|
|
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|
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|
|
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|
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|
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|
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|
-0edb : 65000000;
|
|
-0edc : 41545220;
|
|
-0edd : 00000000;
|
|
-0ede : 58442000;
|
|
-0edf : 300a0000;
|
|
-0ee0 : 58464420;
|
|
-0ee1 : 00000000;
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|
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|
|
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|
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|
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|
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|
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|
|
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|
|
-0ee9 : 53442000;
|
|
-0eea : 44442000;
|
|
-0eeb : 44495220;
|
|
-0eec : 00000000;
|
|
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|
|
-0eee : 64697220;
|
|
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|
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|
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|
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|
|
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|
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|
|
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|
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|
-0efd : 00000000;
|
|
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|
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|
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|
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|
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|
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|
-0f0a : 0a44323a;
|
|
-0f0b : 00000000;
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|
-0f0c : 0a44333a;
|
|
-0f0d : 00000000;
|
|
-0f0e : 0a44343a;
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|
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|
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|
-0f16 : 616d626f;
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|
-0f17 : 00000000;
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
-0f3c : 53504453;
|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
+0e65 : 00000000;
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
+0e78 : 636d643a;
|
|
+0e79 : 00000000;
|
|
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|
|
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|
|
+0e7c : 53504453;
|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
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|
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|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
+0e8f : 2e415452;
|
|
+0e90 : 00000000;
|
|
+0e91 : 61746172;
|
|
+0e92 : 69726f6d;
|
|
+0e93 : 2e62696e;
|
|
+0e94 : 00000000;
|
|
+0e95 : 53746174;
|
|
+0e96 : 3a000000;
|
|
+0e97 : 3a646f6e;
|
|
+0e98 : 650a0000;
|
|
+0e99 : 53656374;
|
|
+0e9a : 6f723a00;
|
|
+0e9b : 20726563;
|
|
+0e9c : 65697665;
|
|
+0e9d : 3a000000;
|
|
+0e9e : 2073656e;
|
|
+0e9f : 64696e67;
|
|
+0ea0 : 0a000000;
|
|
+0ea1 : 64617461;
|
|
+0ea2 : 20000000;
|
|
+0ea3 : 626f6f74;
|
|
+0ea4 : 20000000;
|
|
+0ea5 : 6e616d65;
|
|
+0ea6 : 20000000;
|
|
+0ea7 : 6e756d74;
|
|
+0ea8 : 6f627566;
|
|
+0ea9 : 66657220;
|
|
+0eaa : 00000000;
|
|
+0eab : 00000000;
|
|
+0eac : 00000000;
|
|
+0ead : 72025f07;
|
|
+0eae : f807a900;
|
|
+0eaf : 8d04038d;
|
|
+0eb0 : 4402a907;
|
|
+0eb1 : 8d0503a9;
|
|
+0eb2 : 708d0a03;
|
|
+0eb3 : a9018d0b;
|
|
+0eb4 : 03850960;
|
|
+0eb5 : 7d8a4820;
|
|
+0eb6 : 53e488d0;
|
|
+0eb7 : fa68aa8c;
|
|
+0eb8 : 8e07ad7d;
|
|
+0eb9 : 07ee8e07;
|
|
+0eba : 60a9938d;
|
|
+0ebb : e202a907;
|
|
+0ebc : 8de302a2;
|
|
+0ebd : 0220da07;
|
|
+0ebe : 954320da;
|
|
+0ebf : 07954435;
|
|
+0ec0 : 43c9fff0;
|
|
+0ec1 : f0caca10;
|
|
+0ec2 : ec3006e6;
|
|
+0ec3 : 45d002e6;
|
|
+0ec4 : 4620da07;
|
|
+0ec5 : a2018144;
|
|
+0ec6 : b545d543;
|
|
+0ec7 : d0edca10;
|
|
+0ec8 : f720d207;
|
|
+0ec9 : 4c9407a9;
|
|
+0eca : 038d0fd2;
|
|
+0ecb : 6ce202ad;
|
|
+0ecc : 8e07cd7f;
|
|
+0ecd : 07d0abee;
|
|
+0ece : 0a03d003;
|
|
+0ecf : ee0b03ad;
|
|
+0ed0 : 7d070d7e;
|
|
+0ed1 : 07d08e20;
|
|
+0ed2 : d2076ce0;
|
|
+0ed3 : 0220da07;
|
|
+0ed4 : 8de00220;
|
|
+0ed5 : da078de1;
|
|
+0ed6 : 022de002;
|
|
+0ed7 : c9fff0ed;
|
|
+0ed8 : a9008d8e;
|
|
+0ed9 : 07f08200;
|
|
+0eda : 0001d20f;
|
|
+0edb : 0001d400;
|
|
+0edc : 0001d401;
|
|
+0edd : 0001d409;
|
|
+0ede : 0001d010;
|
|
+0edf : 0001d301;
|
|
+0ee0 : 0001d300;
|
|
+0ee1 : 0001d20a;
|
|
+0ee2 : 0001d01b;
|
|
+0ee3 : 0001d018;
|
|
+0ee4 : 0001d017;
|
|
+0ee5 : 0001d01a;
|
|
+0ee6 : 0001d403;
|
|
+0ee7 : 0001d402;
|
|
+0ee8 : 0001d40e;
|
|
+0ee9 : 0004007c;
|
|
+0eea : 00040078;
|
|
+0eeb : 00040074;
|
|
+0eec : 00040068;
|
|
+0eed : 00040060;
|
|
+0eee : 0004005c;
|
|
+0eef : 00040058;
|
|
+0ef0 : 00040054;
|
|
+0ef1 : 00040050;
|
|
+0ef2 : 0004004c;
|
|
+0ef3 : 00040048;
|
|
+0ef4 : 00040044;
|
|
+0ef5 : 00040040;
|
|
+0ef6 : 0004002c;
|
|
+0ef7 : 00040028;
|
|
+0ef8 : 00040024;
|
|
+0ef9 : 00040020;
|
|
+0efa : 0004001c;
|
|
+0efb : 00040018;
|
|
+0efc : 00040014;
|
|
+0efd : 00040010;
|
|
+0efe : 0004000c;
|
|
+0eff : 00040008;
|
|
+0f00 : 00040004;
|
|
+0f01 : 00040000;
|
|
END;
|
|
diff -ur atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl atari800core_v1_20140312_mist/zpu_config_regs.vhdl
|
|
--- atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl 2014-02-02 19:12:56.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/zpu_config_regs.vhdl 2014-03-09 18:09:38.000000000 +0000
|
|
@@ -46,11 +46,16 @@
|
|
-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
|
|
PAL : OUT STD_LOGIC;
|
|
USE_SDRAM : OUT STD_LOGIC;
|
|
- RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
|
|
+ RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);
|
|
VGA : OUT STD_LOGIC;
|
|
COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
|
|
GPIO_ENABLE : OUT STD_LOGIC;
|
|
- ROM_SELECT : out stD_logic_vector(1 downto 0);
|
|
+ ROM_SELECT : out stD_logic_vector(3 downto 0);
|
|
+
|
|
+ -- sector buffer
|
|
+ sector : out std_logic_vector(31 downto 0);
|
|
+ sector_request : out std_logic;
|
|
+ sector_ready : in std_logic;
|
|
|
|
-- system reset/halt
|
|
PLL_LOCKED : IN STD_LOGIC; -- pll locked
|
|
@@ -161,10 +166,10 @@
|
|
|
|
signal config_6502_next : std_logic_vector(7 downto 0);
|
|
signal config_6502_reg : std_logic_vector(7 downto 0);
|
|
- signal ram_select_next : std_logic_vector(1 downto 0);
|
|
- signal ram_select_reg : std_logic_vector(1 downto 0);
|
|
- signal rom_select_next : std_logic_vector(1 downto 0);
|
|
- signal rom_select_reg : std_logic_vector(1 downto 0);
|
|
+ signal ram_select_next : std_logic_vector(3 downto 0);
|
|
+ signal ram_select_reg : std_logic_vector(3 downto 0);
|
|
+ signal rom_select_next : std_logic_vector(3 downto 0);
|
|
+ signal rom_select_reg : std_logic_vector(3 downto 0);
|
|
signal gpio_enable_next : std_logic;
|
|
signal gpio_enable_reg : std_logic;
|
|
|
|
@@ -207,6 +212,12 @@
|
|
signal zpu_hex_reg : std_logic_vector(15 downto 0);
|
|
|
|
signal pokey_data_out : std_logic_vector(7 downto 0);
|
|
+
|
|
+ signal sector_next : std_logic_vector(31 downto 0);
|
|
+ signal sector_reg : std_logic_vector(31 downto 0);
|
|
+ signal sector_request_next : std_logic;
|
|
+ signal sector_request_reg : std_logic; -- cleared when ready asserted
|
|
+
|
|
begin
|
|
-- register
|
|
process(clk,pll_locked)
|
|
@@ -214,8 +225,8 @@
|
|
if (clk'event and clk='1') then
|
|
if (pll_locked = '0') then
|
|
config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
|
|
- rom_select_reg <= "01";
|
|
- ram_select_reg <= "10";
|
|
+ rom_select_reg <= "0010";
|
|
+ ram_select_reg <= "0010";
|
|
gpio_enable_reg <= '0';
|
|
pause_reg <= (others=>'0');
|
|
paused_reg <= '0';
|
|
@@ -230,6 +241,9 @@
|
|
reset_n_reg <= '0';
|
|
reset_zpu_reg <= '1';
|
|
reset_6502_cpu_reg <= '1';
|
|
+
|
|
+ sector_reg <= (others=>'0');
|
|
+ sector_request_reg <= '0';
|
|
else
|
|
config_6502_reg <= config_6502_next;
|
|
rom_select_reg <= rom_select_next;
|
|
@@ -248,6 +262,9 @@
|
|
reset_n_reg <= reset_n_next;
|
|
reset_zpu_reg <= reset_zpu_next;
|
|
reset_6502_cpu_reg <= reset_6502_cpu_next;
|
|
+
|
|
+ sector_reg <= sector_next;
|
|
+ sector_request_reg <= sector_request_next;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
@@ -328,12 +345,15 @@
|
|
-- R(32 bits) 0=DE1
|
|
-- HEX digits
|
|
-- W(16 bits)
|
|
+ -- SECTOR
|
|
+ -- W(32 bits) - write here initiates a request_reset_zpu
|
|
+ -- R: 0=request_active
|
|
|
|
-- TODO, ROM select, RAM select etc etc
|
|
-- TODO firmware with OSD!
|
|
|
|
-- Writes to registers
|
|
- process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
|
|
+ process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
|
|
begin
|
|
config_6502_next <= config_6502_reg;
|
|
rom_select_next <= rom_select_reg;
|
|
@@ -350,6 +370,9 @@
|
|
|
|
zpu_hex_next <= zpu_hex_reg;
|
|
|
|
+ sector_next <= sector_reg;
|
|
+ sector_request_next <= sector_request_reg and not(sector_ready);
|
|
+
|
|
paused_next <= '0';
|
|
if (not(pause_reg = X"00000000")) then
|
|
pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
|
|
@@ -359,8 +382,8 @@
|
|
if (wr_en = '1' and addr(4) = '0') then
|
|
if(addr_decoded(0) = '1') then
|
|
config_6502_next <= cpu_data_in(7 downto 0);
|
|
- ram_select_next <= cpu_DATA_IN(9 downto 8);
|
|
- rom_select_next <= cpu_DATA_IN(13 downto 12);
|
|
+ ram_select_next <= cpu_DATA_IN(11 downto 8);
|
|
+ rom_select_next <= cpu_DATA_IN(15 downto 12);
|
|
gpio_enable_next <= cpu_DATA_IN(16);
|
|
end if;
|
|
|
|
@@ -396,19 +419,24 @@
|
|
zpu_hex_next <= cpu_data_in(15 downto 0);
|
|
end if;
|
|
|
|
+ if(addr_decoded(11) = '1') then
|
|
+ sector_next <= cpu_data_in;
|
|
+ sector_request_next <= '1';
|
|
+ end if;
|
|
+
|
|
end if;
|
|
end process;
|
|
|
|
-- Read from registers
|
|
- process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
|
|
+ process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
|
|
begin
|
|
data_out <= (others=>'0');
|
|
|
|
if (addr(4) = '0') then
|
|
if (addr_decoded(0) = '1') then
|
|
data_out(7 downto 0) <= config_6502_reg;
|
|
- data_out(9 downto 8) <= ram_select_reg;
|
|
- data_out(13 downto 12) <= rom_select_reg;
|
|
+ data_out(11 downto 8) <= ram_select_reg;
|
|
+ data_out(15 downto 12) <= rom_select_reg;
|
|
data_out(16) <= gpio_enable_reg;
|
|
end if;
|
|
|
|
@@ -451,6 +479,11 @@
|
|
if (addr_decoded(10) = '1') then
|
|
data_out(15 downto 0) <= zpu_hex_reg;
|
|
end if;
|
|
+
|
|
+ if (addr_decoded(11) = '1') then
|
|
+ data_out(0) <= sector_request_reg;
|
|
+ end if;
|
|
+
|
|
else
|
|
data_out(7 downto 0) <= pokey_data_out;
|
|
end if;
|
|
@@ -480,6 +513,7 @@
|
|
SDCARD_DAT3 <= spi_chip_select(0);
|
|
|
|
PAL <= '1'; -- TODO
|
|
+ --USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
|
|
USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
|
|
RAM_SELECT <= ram_select_reg;
|
|
VGA <= '1';
|
|
@@ -496,6 +530,9 @@
|
|
throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled
|
|
|
|
zpu_hex <= zpu_hex_reg;
|
|
+
|
|
+ sector <= sector_reg;
|
|
+ sector_request <= sector_request_reg;
|
|
end vhdl;
|
|
|
|
|
|
diff -ur atari800core_v1_20140121_mcc216/zpu_glue.vhdl atari800core_v1_20140312_mist/zpu_glue.vhdl
|
|
--- atari800core_v1_20140121_mcc216/zpu_glue.vhdl 2014-01-20 20:41:50.000000000 +0000
|
|
+++ atari800core_v1_20140312_mist/zpu_glue.vhdl 2014-03-06 06:02:49.000000000 +0000
|
|
@@ -24,6 +24,7 @@
|
|
ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
|
|
ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
|
|
ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack
|
|
+ ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
|
ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
|
|
|
|
ZPU_DO : out std_logic_vector(31 downto 0);
|
|
@@ -43,7 +44,7 @@
|
|
|
|
-- stack request
|
|
ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
|
|
-
|
|
+
|
|
-- response
|
|
MEMORY_READY : in std_logic
|
|
);
|
|
@@ -114,22 +115,27 @@
|
|
signal config_mem : std_logic;
|
|
signal special_mem : std_logic;
|
|
|
|
- signal result_next : std_logic_vector(3 downto 0);
|
|
- signal result_reg : std_logic_vector(3 downto 0);
|
|
- constant result_external : std_logic_vector(3 downto 0) := "0000";
|
|
- constant result_ram : std_logic_vector(3 downto 0) := "0001";
|
|
- constant result_ram_8bit_0 : std_logic_vector(3 downto 0) := "0010";
|
|
- constant result_ram_8bit_1 : std_logic_vector(3 downto 0) := "0011";
|
|
- constant result_ram_8bit_2 : std_logic_vector(3 downto 0) := "0100";
|
|
- constant result_ram_8bit_3 : std_logic_vector(3 downto 0) := "0101";
|
|
- constant result_rom : std_logic_vector(3 downto 0) := "0110";
|
|
- constant result_rom_8bit_0 : std_logic_vector(3 downto 0) := "0111";
|
|
- constant result_rom_8bit_1 : std_logic_vector(3 downto 0) := "1000";
|
|
- constant result_rom_8bit_2 : std_logic_vector(3 downto 0) := "1001";
|
|
- constant result_rom_8bit_3 : std_logic_vector(3 downto 0) := "1010";
|
|
- constant result_config : std_logic_vector(3 downto 0) := "1011";
|
|
- constant result_external_special : std_logic_vector(3 downto 0) := "1100";
|
|
-
|
|
+ signal result_next : std_logic_vector(4 downto 0);
|
|
+ signal result_reg : std_logic_vector(4 downto 0);
|
|
+ constant result_external : std_logic_vector(4 downto 0) := "00000";
|
|
+ constant result_ram : std_logic_vector(4 downto 0) := "00001";
|
|
+ constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
|
|
+ constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
|
|
+ constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
|
|
+ constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
|
|
+ constant result_rom : std_logic_vector(4 downto 0) := "00110";
|
|
+ constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
|
|
+ constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
|
|
+ constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
|
|
+ constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";
|
|
+ constant result_config : std_logic_vector(4 downto 0) := "01011";
|
|
+ constant result_external_special : std_logic_vector(4 downto 0) := "01100";
|
|
+ constant result_sec : std_logic_vector(4 downto 0) := "01101";
|
|
+ constant result_sec_8bit_0 : std_logic_vector(4 downto 0) := "01110";
|
|
+ constant result_sec_8bit_1 : std_logic_vector(4 downto 0) := "01111";
|
|
+ constant result_sec_8bit_2 : std_logic_vector(4 downto 0) := "10000";
|
|
+ constant result_sec_8bit_3 : std_logic_vector(4 downto 0) := "10001";
|
|
+
|
|
signal request_type : std_logic_vector(4 downto 0);
|
|
|
|
signal zpu_di_use : std_logic_vector(31 downto 0);
|
|
@@ -196,7 +202,8 @@
|
|
ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
|
|
process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
|
|
zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
|
|
- zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp
|
|
+ zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
|
|
+ special_mem
|
|
)
|
|
begin
|
|
zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
|
|
@@ -234,19 +241,37 @@
|
|
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
|
|
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;
|
|
when "01010" =>
|
|
- if (zpu_8bit_read_enable_temp='1') then
|
|
- case (zpu_addr_unsigned(1 downto 0)) is
|
|
- when "00" =>
|
|
- result_next <= result_rom_8bit_3;
|
|
- when "01" =>
|
|
- result_next <= result_rom_8bit_2;
|
|
- when "10" =>
|
|
- result_next <= result_rom_8bit_1;
|
|
- when "11" =>
|
|
- result_next <= result_rom_8bit_0;
|
|
- end case;
|
|
+ -- TODO - addr(14) should just feed 1 bit in result reg!
|
|
+ if (zpu_addr_unsigned(14) = '1') then
|
|
+ if (zpu_8bit_read_enable_temp='1') then
|
|
+ case (zpu_addr_unsigned(1 downto 0)) is
|
|
+ when "00" =>
|
|
+ result_next <= result_sec_8bit_0;
|
|
+ when "01" =>
|
|
+ result_next <= result_sec_8bit_1;
|
|
+ when "10" =>
|
|
+ result_next <= result_sec_8bit_2;
|
|
+ when "11" =>
|
|
+ result_next <= result_sec_8bit_3;
|
|
+ end case;
|
|
+ else
|
|
+ result_next <= result_sec;
|
|
+ end if;
|
|
else
|
|
- result_next <= result_rom;
|
|
+ if (zpu_8bit_read_enable_temp='1') then
|
|
+ case (zpu_addr_unsigned(1 downto 0)) is
|
|
+ when "00" =>
|
|
+ result_next <= result_rom_8bit_3;
|
|
+ when "01" =>
|
|
+ result_next <= result_rom_8bit_2;
|
|
+ when "10" =>
|
|
+ result_next <= result_rom_8bit_1;
|
|
+ when "11" =>
|
|
+ result_next <= result_rom_8bit_0;
|
|
+ end case;
|
|
+ else
|
|
+ result_next <= result_rom;
|
|
+ end if;
|
|
end if;
|
|
ZPU_MEM_BUSY <= '1';
|
|
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
|
|
@@ -287,7 +312,7 @@
|
|
end process;
|
|
|
|
zpu_di_next <= zpu_di;
|
|
- process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
|
|
+ process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di, zpu_sector_di)
|
|
begin
|
|
zpu_di_use <= (others=>'0');
|
|
case result_reg is
|
|
@@ -315,6 +340,16 @@
|
|
zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
|
|
when result_ram_8bit_3 =>
|
|
zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);
|
|
+ when result_sec =>
|
|
+ zpu_di_use <= zpu_sector_DI;
|
|
+ when result_sec_8bit_0 =>
|
|
+ zpu_di_use(7 downto 0) <= zpu_sector_DI(7 downto 0);
|
|
+ when result_sec_8bit_1 =>
|
|
+ zpu_di_use(7 downto 0) <= zpu_sector_DI(15 downto 8);
|
|
+ when result_sec_8bit_2 =>
|
|
+ zpu_di_use(7 downto 0) <= zpu_sector_DI(23 downto 16);
|
|
+ when result_sec_8bit_3 =>
|
|
+ zpu_di_use(7 downto 0) <= zpu_sector_DI(31 downto 24);
|
|
when result_config =>
|
|
zpu_di_use <= zpu_config_di;
|
|
when others =>
|