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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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use work.Replay_Pack.all;
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entity Replay_tb is
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end;
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architecture rtl of Replay_tb is
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-- SYSCLK=4436250Hz, Nsys=1183, Msys=300, Psys=1 ... VIDCLK=27035651Hz, Nvid=2275, Mvid=284, Pvid=8
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constant CLK_A_PERIOD : time := 1 us / (4*4*7.11631);
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constant CLK_B_PERIOD : time := 1 us / 49.152 ;
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constant CLK_C_PERIOD : time := 1 us / 27.010289;
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constant PS2BITTIME : time := 60 uS;
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constant SPIBITTIME : time := 40.00 ns;
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--constant PS2BITTIME : time := 10 uS;
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signal rs232_rxd : bit1;
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signal rs232_txd : bit1;
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signal rs232_cts : bit1;
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signal rs232_rts : bit1;
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signal joy_a : word( 5 downto 0);
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signal joy_b : word( 5 downto 0);
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signal io : word(54 downto 0);
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signal aux_io : word(39 downto 0);
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signal aux_ip : word(22 downto 0);
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signal mem_addr : word(14 downto 0);
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signal mem_dq : word(15 downto 0);
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signal mem_dqs : word(1 downto 0);
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signal mem_dm : word(1 downto 0);
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-- signal mem_udqs : bit1; -- Ctrl8
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-- signal mem_ldqs : bit1; -- Ctrl7
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-- signal mem_udm : bit1; -- Ctrl6
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-- signal mem_ldm : bit1; -- Ctrl5
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signal mem_cs : bit1; -- Ctrl4
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signal mem_ras : bit1; -- Ctrl3
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signal mem_cas : bit1; -- Ctrl2
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signal mem_we : bit1; -- Ctrl1
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signal mem_cke : bit1; -- Ctrl0
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signal mem_clk_p : bit1;
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signal mem_clk_n : bit1;
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signal disk_led : bit1;
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signal pwr_led : bit1;
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signal Ext_Rst_L : bit1;
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signal b2v5_io_1 : bit1;
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signal b2v5_io_0 : bit1;
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signal video_clk_p : bit1;
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signal video_clk_n : bit1;
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signal video_rst_l : bit1;
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signal video_int : bit1;
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signal video_de : bit1;
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signal video_v : bit1;
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signal video_h : bit1;
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signal video_data : word(11 downto 0); --Video11..0
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signal video_ddc_clk : bit1;
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signal video_ddc_data : bit1;
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signal video_hsync : bit1;
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signal video_vsync : bit1;
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signal video_spc : bit1;
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signal video_spd : bit1;
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signal audio_lrcin : bit1;
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signal audio_mclk : bit1;
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signal audio_bckin : bit1;
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signal audio_din : bit1;
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signal ps2_clk : word(1 downto 0);
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signal ps2_data : word(1 downto 0);
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signal scl : bit1;
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signal sda : bit1;
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signal fpga_ctrl : word(1 downto 0);
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signal fpga_spi_clk : bit1;
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signal fpga_spi_mosi : bit1;
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signal fpga_spi_miso : bit1;
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--signal ssc_tf : bit1;
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--signal ssc_td : bit1;
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--signal ssc_rk : bit1;
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--signal ssc_rd : bit1;
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signal clk_68k : bit1;
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signal clk_aux : bit1;
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signal clk_a : bit1;
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signal clk_b : bit1;
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signal clk_c : bit1;
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--
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signal por : bit1;
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signal por_l : bit1;
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signal ps2_clk_drive_tx : word(1 downto 0) := "11";
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signal ps2_data_drive_tx : word(1 downto 0) := "11";
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signal ps2_clk_drive_rx : word(1 downto 0) := "11";
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signal ps2_data_drive_rx : word(1 downto 0) := "11";
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signal ps2_send_active : word(1 downto 0) := "00";
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signal ps2_slave_rx : bit1;
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signal ps2_slave_data : word(8 downto 0);
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--{{{
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component ddr
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port (
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DQ : inout std_logic_vector(15 downto 0);
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DQS : inout std_logic_vector( 1 downto 0);
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ADDR : in std_logic_vector(12 downto 0);
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BA : in std_logic_vector( 1 downto 0);
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CLK : in std_logic;
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CLK_N : in std_logic;
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CKE : in std_logic;
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CS_N : in std_logic;
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RAS_N : in std_logic;
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CAS_N : in std_logic;
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WE_N : in std_logic;
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DM : in std_logic_vector( 1 downto 0)
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);
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end component;
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--}}}
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begin
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p_clk_gen_a : process
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begin
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clk_a <= '1';
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wait for CLK_A_PERIOD/2;
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clk_a <= '0';
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wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
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end process;
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p_clk_gen_b : process
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begin
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clk_b <= '1';
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wait for CLK_B_PERIOD/2;
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clk_b <= '0';
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wait for CLK_B_PERIOD - (CLK_B_PERIOD/2 );
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end process;
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p_clk_gen_c : process
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begin
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clk_c <= '1';
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wait for CLK_C_PERIOD/2;
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clk_c <= '0';
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wait for CLK_C_PERIOD - (CLK_C_PERIOD/2 );
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end process;
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p_rst : process
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begin
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por <= '1'; por_l <= '0';
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wait until rising_edge(clk_c);
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wait until rising_edge(clk_c);
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wait until rising_edge(clk_c);
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wait until rising_edge(clk_c);
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por <= '0'; por_l <= '1';
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wait;
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end process;
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Ext_Rst_L <= por_l;
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-- core
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u_Replay : entity work.Replay_Top
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port map (
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-- RS232 debug port
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i_RS232_RXD => rs232_rxd,
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o_RS232_TXD => rs232_txd,
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i_RS232_CTS => rs232_cts,
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o_RS232_RTS => rs232_rts,
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-- Joysticks
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i_Joy_A => joy_a,
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i_Joy_B => joy_b,
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-- IO
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b_IO => io,
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b_Aux_IO => aux_io,
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i_Aux_IP => aux_ip,
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-- DRAM
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o_Mem_Addr => mem_addr,
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b_Mem_DQ => mem_dq,
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b_Mem_UDQS => mem_dqs(1), --mem_udqs,
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b_Mem_LDQS => mem_dqs(0), --mem_ldqs,
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o_Mem_UDM => mem_dm(1), --mem_udm,
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o_Mem_LDM => mem_dm(0), --mem_ldm,
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o_Mem_CS => mem_cs,
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o_Mem_RAS => mem_ras,
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o_Mem_CAS => mem_cas,
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o_Mem_WE => mem_we,
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o_Mem_CKE => mem_cke,
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o_Mem_Clk_P => mem_clk_p,
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o_Mem_Clk_N => mem_clk_n,
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--
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o_Disk_Led => disk_led,
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o_Pwr_Led => pwr_led,
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--
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i_Ext_Rst_L => Ext_Rst_L,
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b_2V5_IO_1 => b2v5_io_1,
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b_2V5_IO_0 => b2v5_io_0,
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-- Video
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o_Video_Clk_P => video_clk_p,
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o_Video_Clk_N => video_clk_n,
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o_Video_Rst_L => video_rst_l,
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i_Video_Int => video_int,
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o_Video_DE => video_de,
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o_Video_V => video_v,
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o_Video_H => video_h,
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o_Video_Data => video_data,
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b_Video_DDC_Clk => video_ddc_clk,
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b_Video_DDC_Data => video_ddc_data,
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o_Video_HSync => video_hsync,
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o_Video_VSync => video_vsync,
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b_Video_SPC => video_spc,
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b_Video_SPD => video_spd,
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-- Audio
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o_Audio_LRCIN => audio_lrcin,
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o_Audio_MCLK => audio_mclk,
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o_Audio_BCKIN => audio_bckin,
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o_Audio_DIN => audio_din,
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--
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b_PS2A_Clk => ps2_clk(0),
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b_PS2A_Data => ps2_data(0),
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b_PS2B_Clk => ps2_clk(1),
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b_PS2B_Data => ps2_data(1),
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b_SCL => scl,
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b_SDA => sda,
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-- System control
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i_FPGA_Ctrl0 => fpga_ctrl(0),
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i_FPGA_Ctrl1 => fpga_ctrl(1),
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i_FPGA_SPI_Clk => fpga_spi_clk,
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b_FPGA_SPI_MOSI => fpga_spi_mosi,
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b_FPGA_SPI_MISO => fpga_spi_miso,
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-- SSC & config pins
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--i_SSC_TF => ssc_tf,
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--i_SSC_TD => ssc_td,
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--o_SSC_RK => ssc_rk,
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--o_SSC_RD => ssc_rd,
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o_SSC_RD => open,
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-- Clocks
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o_Clk_68K => clk_68k,
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b_Clk_Aux => clk_aux,
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ClK_A => clk_a,
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ClK_B => clk_b,
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ClK_C => clk_c
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);
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rs232_rxd <= '0';
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rs232_cts <= '0';
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joy_a <= "000000";
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joy_b <= "000000";
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io <= (others => 'Z');
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aux_io <= (others => 'Z');
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aux_ip <= (others => '0');
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mem_dq <= (others => 'Z');
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mem_dqs <= "ZZ";
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-- mem_udqs <= 'Z';
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-- mem_ldqs <= 'Z';
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b2v5_io_1 <= 'Z';
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b2v5_io_0 <= 'Z';
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video_int <= '0';
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video_ddc_clk <= '0';
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video_ddc_data <= '0';
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clk_aux <= 'Z';
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p_i2c_test : process
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-- chrontel
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-- EC write 1110110x
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-- ED read
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constant I2CBITTIME : time := 2.5 uS;
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procedure I2CStart is
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begin
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scl <= 'H';
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sda <= 'H';
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-- start bit
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wait for I2CBITTIME/4;
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sda <= '0';
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wait for I2CBITTIME/4;
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end procedure;
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procedure I2CReStart is
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begin
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scl <= '0';
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sda <= 'H';
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wait for I2CBITTIME/2;
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scl <= 'H';
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wait for I2CBITTIME/4;
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sda <= '0';
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wait for I2CBITTIME/4;
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scl <= '0';
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end procedure;
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procedure I2CStop is
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begin
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sda <= '0';
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scl <= '0';
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wait for I2CBITTIME/2;
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scl <= 'H';
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wait for I2CBITTIME/2;
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sda <= 'H';
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wait for I2CBITTIME/2;
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end procedure;
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procedure I2CWaitAck is
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begin
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sda <= 'H';
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scl <= '0';
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wait for I2CBITTIME/2;
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scl <= 'H';
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wait for I2CBITTIME/2;
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end procedure;
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procedure I2CNAck is
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begin
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sda <= 'H';
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scl <= '0';
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wait for I2CBITTIME/2;
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scl <= 'H';
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wait for I2CBITTIME/2;
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end procedure;
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procedure I2CWrite (data:word(7 downto 0)) is
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begin
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for i in 7 downto 0 loop
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scl <= '0';
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wait for I2CBITTIME/4;
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if (data(i) = '1') then sda <= 'H'; else sda <= '0'; end if;
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wait for I2CBITTIME/4;
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scl <= 'H';
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wait for I2CBITTIME/2;
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end loop;
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end procedure;
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procedure I2CRead is
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variable read_data : word(7 downto 0);
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begin
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for i in 7 downto 0 loop
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scl <= '0';
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wait for I2CBITTIME/4;
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read_data(i) := sda;
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sda <= 'H';
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wait for I2CBITTIME/4;
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scl <= 'H';
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wait for I2CBITTIME/2;
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end loop;
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assert false report
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"I2C Read : " ; --& to_string(to_bitvector(read_data), "%2x");
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end procedure;
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begin
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scl <= 'H';
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sda <= 'H';
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video_spc <= 'H';
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video_spd <= 'H';
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wait for 5 us;
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-- write
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I2CStart;
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I2CWrite(x"EC"); -- addr
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I2CWaitAck;
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I2CWrite(x"81"); -- sub addr
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I2CWaitAck;
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I2CWrite(x"12"); -- data
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I2CWaitAck;
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I2CStop;
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wait for 5 us;
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-- read
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I2CStart;
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I2CWrite(x"EC"); -- addr
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I2CWaitAck;
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I2CWrite(x"81"); -- sub addr
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I2CWaitAck;
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I2CReStart; -- restart
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I2CWrite(x"ED"); -- addr
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I2CWaitAck;
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I2CRead;
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I2CNAck;
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I2CStop;
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wait;
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end process;
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--
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-- dummy i2c slave
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u_slave : entity work.Replay_I2C_CH7301
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port map (
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i_Rst => por,
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b_SPC => video_spc,
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b_SPD => video_spd
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);
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--
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--
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p_spi_test : process
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procedure SPI (data:word(7 downto 0)) is
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variable read_data : word(7 downto 0);
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begin
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wait for SPIBITTIME/4;
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for i in 7 downto 0 loop
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fpga_spi_clk <= '1';
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wait for SPIBITTIME/4;
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if (data(i) = '1') then fpga_spi_mosi <= '1'; else fpga_spi_mosi <= '0'; end if;
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wait for SPIBITTIME/4;
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fpga_spi_clk <= '0';
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wait for SPIBITTIME/2;
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fpga_spi_clk <= '1';
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read_data(i) := fpga_spi_miso;
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end loop;
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fpga_spi_clk <= '1';
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wait for SPIBITTIME;
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assert false report
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"SPI Read : "; -- & to_string(to_bitvector(read_data), "%2x");
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--wait for 1 us;
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end procedure;
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procedure Ena(sel:integer) is
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begin
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case sel is
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--when 0 => fpga_ctrl <= "00";
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when 1 => fpga_ctrl <= "10";
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when 2 => fpga_ctrl <= "01";
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when others => null;
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end case;
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end procedure;
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procedure Dis is
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begin
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fpga_ctrl <= "11";
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end procedure;
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begin
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-- SAM7S CPOL = 1, NCPHA = 0
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-- clock normally high, data change on leading edge of clock, captured on following
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fpga_spi_clk <= '1';
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fpga_spi_mosi <= '0';
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Dis;
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wait for 1 us;
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Ena(2);
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SPI(x"23"); -- set phase
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SPI(x"68");
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SPI(x"02");
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Dis;
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wait for 5 us;
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-- RESET ----------------------------------------------------------
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Ena(2);
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SPI(x"11"); -- soft reset
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Dis;
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wait for 5 us;
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Ena(1);
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SPI(x"80"); -- command set addr
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SPI(x"10");
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SPI(x"00");
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SPI(x"01");
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SPI(x"00");
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Dis;
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wait for 1 us;
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Ena(1);
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SPI(x"81"); -- command
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SPI(x"00"); -- do write
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Dis;
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wait for 1 us;
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Ena(1);
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SPI(x"B0"); -- command
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SPI(x"01"); -- data
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SPI(x"02"); -- data
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SPI(x"03"); -- data
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SPI(x"04"); -- data
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SPI(x"05"); -- data
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SPI(x"06"); -- data
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SPI(x"07"); -- data
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SPI(x"08"); -- data
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SPI(x"09"); -- data
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SPI(x"0A"); -- data
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SPI(x"0B"); -- data
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SPI(x"0C"); -- data
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SPI(x"0D"); -- data
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SPI(x"0E"); -- data
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SPI(x"0F"); -- data
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SPI(x"10"); -- data
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Dis;
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wait for 10 us;
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Ena(1);
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SPI(x"81"); -- command
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SPI(x"80"); -- set up for read
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Dis;
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wait for 1 us;
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Ena(1);
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SPI(x"80"); -- command
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SPI(x"10"); -- command
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SPI(x"00"); -- command
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SPI(x"01"); -- command
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SPI(x"00"); -- command
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Dis;
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wait for 1 us;
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Ena(1);
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SPI(x"84"); -- command
|
|
SPI(x"0F"); -- do read (word len -1)
|
|
SPI(x"00"); -- do read (word len -1)
|
|
Dis;
|
|
wait for 5 us;
|
|
|
|
Ena(1);
|
|
SPI(x"A0"); -- command
|
|
for i in 0 to 15 loop
|
|
SPI(x"00"); -- command
|
|
end loop;
|
|
Dis;
|
|
|
|
-- RESET ----------------------------------------------------------
|
|
|
|
wait for 10 us;
|
|
Ena(2);
|
|
SPI(x"11"); -- command: soft reset active
|
|
Dis;
|
|
wait for 20 us;
|
|
Ena(2);
|
|
SPI(x"10"); -- command: soft reset off
|
|
Dis;
|
|
|
|
-- we check how loading a PRG file works out...
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
SPI(x"08");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"00"); -- ADDR L
|
|
SPI(x"A0"); -- ADDR H
|
|
SPI(x"09"); -- data 00
|
|
SPI(x"A0"); -- data 01
|
|
SPI(x"77"); -- data 02
|
|
SPI(x"A0"); -- data 03
|
|
SPI(x"41"); -- data 04
|
|
SPI(x"30"); -- data 05
|
|
SPI(x"C3"); -- data 06
|
|
SPI(x"C2"); -- data 07
|
|
SPI(x"CD"); -- data 08
|
|
SPI(x"A0"); -- data LDY #$80
|
|
SPI(x"80"); -- data
|
|
SPI(x"99"); -- data STA $4000,Y
|
|
SPI(x"00"); -- data
|
|
SPI(x"40"); -- data
|
|
SPI(x"C8"); -- data INY
|
|
SPI(x"D0"); -- data BNE to STA
|
|
SPI(x"FA"); -- data
|
|
SPI(x"A0"); -- data LDY #$80
|
|
SPI(x"80"); -- data
|
|
SPI(x"B9"); -- data LDA $4000,Y
|
|
SPI(x"00"); -- data
|
|
SPI(x"40"); -- data
|
|
SPI(x"C8"); -- data INY
|
|
SPI(x"D0"); -- data BNE to LDA
|
|
SPI(x"FA"); -- data
|
|
SPI(x"4C"); -- data
|
|
SPI(x"2F"); -- data
|
|
SPI(x"FD"); -- data
|
|
Dis;
|
|
wait for 30 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"80"); -- set up for read
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- addr
|
|
SPI(x"00"); --
|
|
SPI(x"A0"); --
|
|
SPI(x"00"); --
|
|
SPI(x"00"); --
|
|
Dis;
|
|
|
|
wait for 1 us;
|
|
Ena(1);
|
|
SPI(x"84"); -- command
|
|
SPI(x"0F"); -- do read (word len -1)
|
|
SPI(x"00"); -- do read (word len -1)
|
|
Dis;
|
|
wait for 5 us;
|
|
|
|
Ena(1);
|
|
SPI(x"A0"); -- command
|
|
for i in 0 to 15 loop
|
|
SPI(x"00"); -- command
|
|
end loop;
|
|
Dis;
|
|
|
|
-- RESET ----------------------------------------------------------
|
|
|
|
wait for 10 us;
|
|
Ena(2);
|
|
SPI(x"11"); -- command: soft reset active
|
|
Dis;
|
|
wait for 20 us;
|
|
Ena(2);
|
|
SPI(x"10"); -- command: soft reset off
|
|
Dis;
|
|
|
|
-- we check how loading a BIN file works out... (1541)
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"00");
|
|
SPI(x"80");
|
|
SPI(x"04");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"00"); -- data
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
-- we check how loading a BIN file works out... (VIC-20)
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"00");
|
|
SPI(x"80");
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"00"); -- data
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 30 us;
|
|
|
|
-- RESET ----------------------------------------------------------
|
|
|
|
wait for 10 us;
|
|
Ena(2);
|
|
SPI(x"11"); -- command: soft reset active
|
|
Dis;
|
|
wait for 20 us;
|
|
Ena(2);
|
|
SPI(x"10"); -- command: soft reset off
|
|
Dis;
|
|
|
|
-- we check how loading a d64 file works out...
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"A0");
|
|
SPI(x"65");
|
|
SPI(x"01");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"f0");
|
|
SPI(x"AA");
|
|
SPI(x"02");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
-- do again, check how reload works
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"A0");
|
|
SPI(x"65");
|
|
SPI(x"01");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"01"); -- data
|
|
SPI(x"02"); -- data
|
|
SPI(x"03"); -- data
|
|
SPI(x"04"); -- data
|
|
SPI(x"05"); -- data
|
|
SPI(x"06"); -- data
|
|
SPI(x"07"); -- data
|
|
SPI(x"08"); -- data
|
|
SPI(x"09"); -- data
|
|
SPI(x"0A"); -- data
|
|
SPI(x"0B"); -- data
|
|
SPI(x"0C"); -- data
|
|
SPI(x"0D"); -- data
|
|
SPI(x"0E"); -- data
|
|
SPI(x"0F"); -- data
|
|
SPI(x"10"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
Ena(1);
|
|
SPI(x"80"); -- command set addr
|
|
SPI(x"00");
|
|
SPI(x"26");
|
|
SPI(x"01");
|
|
SPI(x"00");
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"81"); -- command
|
|
SPI(x"00"); -- do write
|
|
Dis;
|
|
wait for 1 us;
|
|
|
|
Ena(1);
|
|
SPI(x"B0"); -- command
|
|
SPI(x"A1"); -- data
|
|
SPI(x"A2"); -- data
|
|
SPI(x"A3"); -- data
|
|
SPI(x"A4"); -- data
|
|
SPI(x"A5"); -- data
|
|
SPI(x"A6"); -- data
|
|
SPI(x"A7"); -- data
|
|
SPI(x"A8"); -- data
|
|
SPI(x"A9"); -- data
|
|
SPI(x"AA"); -- data
|
|
SPI(x"AB"); -- data
|
|
SPI(x"AC"); -- data
|
|
SPI(x"AD"); -- data
|
|
SPI(x"AE"); -- data
|
|
SPI(x"AF"); -- data
|
|
SPI(x"B0"); -- data
|
|
Dis;
|
|
wait for 10 us;
|
|
|
|
wait;
|
|
end process;
|
|
|
|
p_ps2 : process
|
|
|
|
procedure PS2Write (dst : integer; data:word(7 downto 0)) is
|
|
variable parity : bit1;
|
|
begin
|
|
-- wait for high clock
|
|
while (ps2_clk(dst) = '0') loop
|
|
wait for PS2BITTIME;
|
|
end loop;
|
|
ps2_send_active(dst) <= '1';
|
|
-- start
|
|
ps2_data_drive_tx(dst) <= '0';
|
|
wait for PS2BITTIME/4;
|
|
ps2_clk_drive_tx(dst) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
ps2_clk_drive_tx(dst) <= '1';
|
|
|
|
parity := '0';
|
|
for i in 0 to 7 loop
|
|
wait for PS2BITTIME/4;
|
|
if (data(i) = '1') then ps2_data_drive_tx(dst) <= '1'; else ps2_data_drive_tx(dst) <= '0'; end if;
|
|
parity := parity xor data(i);
|
|
wait for PS2BITTIME/4;
|
|
ps2_clk_drive_tx(dst) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
ps2_clk_drive_tx(dst) <= '1';
|
|
|
|
if (i=3) then
|
|
wait;
|
|
end if;
|
|
end loop;
|
|
-- parity
|
|
--parity := not parity;
|
|
wait for PS2BITTIME/4;
|
|
if (parity = '0') then ps2_data_drive_tx(dst) <= '1'; else ps2_data_drive_tx(dst) <= '0'; end if;
|
|
wait for PS2BITTIME/4;
|
|
ps2_clk_drive_tx(dst) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
ps2_clk_drive_tx(dst) <= '1';
|
|
-- stop
|
|
wait for PS2BITTIME/4;
|
|
ps2_clk_drive_tx(dst) <= '1';
|
|
wait for PS2BITTIME/4;
|
|
ps2_clk_drive_tx(dst) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
ps2_clk_drive_tx(dst) <= '1';
|
|
ps2_send_active(dst) <= '0';
|
|
|
|
end procedure;
|
|
|
|
begin
|
|
ps2_clk_drive_tx(0) <= '1';
|
|
ps2_data_drive_tx(0) <= '1';
|
|
ps2_clk_drive_tx(1) <= '1';
|
|
ps2_data_drive_tx(1) <= '1';
|
|
|
|
wait for 300 us;
|
|
|
|
wait until ps2_slave_rx = '1';
|
|
|
|
wait for 100 us;
|
|
PS2Write(0, x"FA");
|
|
wait for 100 us;
|
|
PS2Write(0, x"AA");
|
|
wait for 100 us;
|
|
PS2Write(0, x"00");
|
|
wait for 100 us;
|
|
--PS2Write(0, x"27");
|
|
|
|
wait for 1 ms;
|
|
PS2Write(0, x"23");
|
|
wait for 300 us;
|
|
PS2Write(0, x"F0");
|
|
wait for 100 us;
|
|
PS2Write(0, x"23");
|
|
wait for 100 us;
|
|
wait;
|
|
end process;
|
|
|
|
ps2_clk_drive_rx(1) <= '1';
|
|
ps2_data_drive_rx(1) <= '1';
|
|
|
|
p_ps2_slave : process
|
|
begin
|
|
wait until falling_edge(ps2_data(0)) and (ps2_send_active(0) = '0');
|
|
|
|
ps2_slave_rx <= '0';
|
|
----
|
|
---- wait;
|
|
----
|
|
ps2_clk_drive_rx(0) <= '1';
|
|
ps2_data_drive_rx(0) <= '1';
|
|
|
|
if (ps2_clk(0) = '0') then
|
|
wait for 1 us;
|
|
-- wait for clock to go high
|
|
while (ps2_clk(0) = '0') loop
|
|
wait for PS2BITTIME/2;
|
|
end loop;
|
|
wait for PS2BITTIME/2;
|
|
|
|
ps2_clk_drive_rx(0) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
|
|
for i in 0 to 8 loop
|
|
ps2_clk_drive_rx(0) <= '1';
|
|
wait for PS2BITTIME/2;
|
|
if (ps2_data(0) = '0') then
|
|
ps2_slave_data <= '0' & ps2_slave_data(7 downto 0);
|
|
else
|
|
ps2_slave_data <= '1' & ps2_slave_data(7 downto 0);
|
|
end if;
|
|
|
|
ps2_clk_drive_rx(0) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
end loop;
|
|
ps2_clk_drive_rx(0) <= '1';
|
|
ps2_data_drive_rx(0) <= '0';
|
|
wait for PS2BITTIME/2;
|
|
ps2_clk_drive_rx(0) <= '0';
|
|
|
|
wait for PS2BITTIME/2;
|
|
ps2_data_drive_rx(0) <= '1';
|
|
ps2_clk_drive_rx(0) <= '1';
|
|
ps2_slave_rx <= '1';
|
|
end if;
|
|
end process;
|
|
|
|
|
|
ps2_clk(0) <= '0' when (ps2_clk_drive_rx(0) = '0') or (ps2_clk_drive_tx(0) = '0') else 'H';
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ps2_data(0) <= '0' when (ps2_data_drive_rx(0) = '0') or (ps2_data_drive_tx(0) = '0') else 'H';
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ps2_clk(1) <= '0' when (ps2_clk_drive_rx(1) = '0') or (ps2_clk_drive_tx(1) = '0') else 'H';
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ps2_data(1) <= '0' when (ps2_data_drive_rx(1) = '0') or (ps2_data_drive_tx(1) = '0') else 'H';
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u_ram : ddr
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port map (
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DQ => mem_dq,
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DQS => mem_dqs,
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-- DQS(1) => mem_udqs,
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-- DQS(0) => mem_ldqs,
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ADDR => mem_addr(12 downto 0),
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BA => mem_addr(14 downto 13),
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CLK => mem_clk_p,
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CLK_N => mem_clk_n,
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CKE => mem_cke,
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CS_N => mem_cs,
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RAS_N => mem_ras,
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CAS_N => mem_cas,
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WE_N => mem_we,
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DM => mem_dm
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-- DM(1) => mem_udm,
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-- DM(0) => mem_ldm
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);
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end;
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