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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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# Date created = 19:35:48 June 01, 2018
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# anticmax_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M02SCU169C8G
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set_global_assignment -name TOP_LEVEL_ENTITY anticmax
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:35:48 JUNE 01, 2018"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_RST
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_INT
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_SDA
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_SCL
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#
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[0]
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[1]
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[2]
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#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[3]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to REF_N
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to REF_N_B
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HALT_N
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HALT_N_B
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set_instance_assignment -name CURRENT_STRENGTH_NEW "4MA" -to REF_N
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set_instance_assignment -name CURRENT_STRENGTH_NEW "4MA" -to HALT_N
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#
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#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[1]
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#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[2]
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#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[3]
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#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[4]
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set_location_assignment PIN_G9 -to CLK_SLOW
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set_location_assignment PIN_H8 -to CLK_OUT
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set_location_assignment PIN_A6 -to NC[1] #PIN1 (VSS)
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set_location_assignment PIN_B5 -to AN[0] #PIN2
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set_location_assignment PIN_A5 -to AN[1] #PIN3
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set_location_assignment PIN_B4 -to LP_N #PIN4
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set_location_assignment PIN_A4 -to AN[2] #PIN5
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set_location_assignment PIN_B3 -to RNMI_N #PIN6
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set_location_assignment PIN_A3 -to NMI_N #PIN7
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set_location_assignment PIN_C1 -to REF_N #PIN8
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set_location_assignment PIN_D1 -to REF_N_B #PIN8
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set_location_assignment PIN_A2 -to HALT_N #PIN9
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set_location_assignment PIN_B2 -to HALT_N_B #PIN9
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set_location_assignment PIN_B1 -to A[3] #PIN10
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set_location_assignment PIN_M1 -to A[2] #PIN11
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set_location_assignment PIN_M2 -to A[1] #PIN12
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set_location_assignment PIN_N2 -to A[0] #PIN13
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set_location_assignment PIN_L3 -to RW_N #PIN14
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set_location_assignment PIN_M3 -to RDY #PIN15
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set_location_assignment PIN_N3 -to RDY_B #PIN15
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set_location_assignment PIN_K5 -to RDY_C #PIN15
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set_location_assignment PIN_M4 -to A[10] #PIN16
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set_location_assignment PIN_N4 -to A[12] #PIN17
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set_location_assignment PIN_M5 -to A[13] #PIN18
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set_location_assignment PIN_N5 -to A[14] #PIN19
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set_location_assignment PIN_N6 -to A[15] #PIN20
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set_location_assignment PIN_M7 -to NC[2] #PIN21 (VCC)
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set_location_assignment PIN_N7 -to A[11] #PIN22
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set_location_assignment PIN_M8 -to A[9] #PIN23
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set_location_assignment PIN_N8 -to A[8] #PIN24
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set_location_assignment PIN_M9 -to A[7] #PIN25
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set_location_assignment PIN_N9 -to A[6] #PIN26
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set_location_assignment PIN_M10 -to A[5] #PIN27
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set_location_assignment PIN_N10 -to A[4] #PIN28
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set_location_assignment PIN_M11 -to PHI2 #PIN29
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set_location_assignment PIN_N11 -to D[0] #PIN30
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set_location_assignment PIN_A12 -to D[1] #PIN31
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set_location_assignment PIN_B11 -to D[2] #PIN32
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set_location_assignment PIN_A11 -to D[3] #PIN33
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set_location_assignment PIN_B10 -to PHI0 #PIN34
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set_location_assignment PIN_A10 -to FO0 #PIN35
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set_location_assignment PIN_A9 -to RST_N #PIN36
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set_location_assignment PIN_A8 -to D[7] #PIN37
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set_location_assignment PIN_B7 -to D[6] #PIN38
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set_location_assignment PIN_A7 -to D[5] #PIN39
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set_location_assignment PIN_B6 -to D[4] #PIN40
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set_location_assignment PIN_L13 -to GPIO[0] #JP1_1
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set_location_assignment PIN_M13 -to GPIO[1] #JP1_2
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set_location_assignment PIN_N12 -to GPIO[2] #JP1_3
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set_location_assignment PIN_K13 -to GPIO[3] #JP2_1
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set_location_assignment PIN_K12 -to GPIO[4] #JP2_2
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set_location_assignment PIN_L12 -to GPIO[5] #JP2_3
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set_location_assignment PIN_C13 -to GPIO[6] #JP3_1
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set_location_assignment PIN_D12 -to GPIO[7] #JP3_2
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set_location_assignment PIN_D13 -to GPIO[8] #JP3_3
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set_location_assignment PIN_B12 -to GPIO[9] #JP4_1
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set_location_assignment PIN_B13 -to GPIO[10] #JP4_2
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set_location_assignment PIN_C12 -to GPIO[11] #JP4_3
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CLK_OUT
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set_global_assignment -name OPTIMIZATION_MODE BALANCED
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set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
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set_global_assignment -name VHDL_FILE simple_counter.vhdl
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set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
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set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
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set_global_assignment -name VHDL_FILE antic_counter.vhdl
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set_global_assignment -name VHDL_FILE antic.vhdl
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set_global_assignment -name VHDL_FILE timing_antic.vhd
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set_global_assignment -name SDC_FILE anticmax.sdc
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set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
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set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
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set_global_assignment -name VHDL_FILE delay_line.vhdl
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set_global_assignment -name VHDL_FILE latch_delay_line.vhdl
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set_global_assignment -name VHDL_FILE phi_mult.vhdl
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set_global_assignment -name VHDL_FILE synchronizer.vhdl
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set_global_assignment -name VHDL_FILE anticmax.vhd
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set_global_assignment -name QIP_FILE int_osc/synthesis/int_osc.qip
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set_global_assignment -name QIP_FILE pll.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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