repo2/mcc216_5200/svideo/sin_cos.vhd @ 1476
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-- Package / Component definition
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-- ===================================================================================
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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PACKAGE sin_cos_pkg IS
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COMPONENT sin_cos
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PORT(
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-- Clock
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clk : IN STD_LOGIC;
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clk_ena : IN STD_LOGIC;
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-- Sine computation
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sin_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sin_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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sin_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
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-- Cosine computation
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cos_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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cos_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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cos_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
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);
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END COMPONENT;
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END PACKAGE;
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-- ===================================================================================
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-- Entity / Architecture definition
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-- ===================================================================================
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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ENTITY sin_cos IS
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PORT(
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-- Clock
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clk : IN STD_LOGIC;
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clk_ena : IN STD_LOGIC;
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-- Sine computation
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sin_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sin_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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sin_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
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-- Cosine computation
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cos_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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cos_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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cos_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
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);
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END sin_cos;
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ARCHITECTURE rtl OF sin_cos IS
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COMPONENT sin_rom IS
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PORT
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(
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clock : IN STD_LOGIC;
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enable : IN STD_LOGIC := '1';
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address_a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
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address_b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
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q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT sin_rom;
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SIGNAL sin_val : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL cos_val : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL sin_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL cos_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
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BEGIN
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sin_inst : sin_rom
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PORT MAP
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(
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clock => clk,
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enable => clk_ena,
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address_a(10 DOWNTO 3) => sin_amp,
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address_a(2) => sin_ph(2) XOR sin_ph(3),
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address_a(1) => sin_ph(1) XOR sin_ph(3),
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address_a(0) => sin_ph(0) XOR sin_ph(3),
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q_a => sin_val(7 DOWNTO 0),
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address_b(10 DOWNTO 3) => cos_amp,
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address_b(2) => cos_ph(2) XOR (NOT cos_ph(3)),
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address_b(1) => cos_ph(1) XOR (NOT cos_ph(3)),
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address_b(0) => cos_ph(0) XOR (NOT cos_ph(3)),
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q_b => cos_val(7 DOWNTO 0)
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);
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sin_val(8) <= '0';
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cos_val(8) <= '0';
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-- Delayed phase for output generation
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sin_ph_dly <= sin_ph WHEN rising_edge(clk);
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cos_ph_dly <= cos_ph WHEN rising_edge(clk);
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-- Output generation using sine and cosine symetries
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sin_cos_gen:
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FOR i IN 0 TO 8 GENERATE
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sin_out(i) <= sin_val(i) XOR sin_ph_dly(4);
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cos_out(i) <= cos_val(i) XOR cos_ph_dly(3) XOR cos_ph_dly(4);
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END GENERATE;
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END rtl;
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