repo2/eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.vhd @ 1476
| 974 | markw | -- clkctrl2.vhd
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-- Generated using ACDS version 18.0 614
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity clkctrl2 is
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port (
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inclk3x : in std_logic := '0'; -- altclkctrl_input.inclk3x
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inclk2x : in std_logic := '0'; -- .inclk2x
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inclk1x : in std_logic := '0'; -- .inclk1x
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inclk0x : in std_logic := '0'; -- .inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => '0'); -- .clkselect
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outclk : out std_logic -- altclkctrl_output.outclk
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);
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end entity clkctrl2;
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architecture rtl of clkctrl2 is
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component clkctrl2_altclkctrl_0 is
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port (
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inclk3x : in std_logic := 'X'; -- inclk3x
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inclk2x : in std_logic := 'X'; -- inclk2x
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inclk1x : in std_logic := 'X'; -- inclk1x
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inclk0x : in std_logic := 'X'; -- inclk0x
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clkselect : in std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
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outclk : out std_logic -- outclk
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);
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end component clkctrl2_altclkctrl_0;
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begin
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altclkctrl_0 : component clkctrl2_altclkctrl_0
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port map (
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inclk3x => inclk3x, -- altclkctrl_input.inclk3x
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inclk2x => inclk2x, -- .inclk2x
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inclk1x => inclk1x, -- .inclk1x
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inclk0x => inclk0x, -- .inclk0x
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clkselect => clkselect, -- .clkselect
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outclk => outclk -- altclkctrl_output.outclk
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);
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end architecture rtl; -- of clkctrl2
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