repo2/atari_chips/sally/cpu_6510.vhd @ 1476
| 1 | markw | -- -----------------------------------------------------------------------
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--
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-- FPGA 64
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--
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-- A fully functional commodore 64 implementation in a single FPGA
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--
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-- -----------------------------------------------------------------------
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-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
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-- http://www.syntiac.com/fpga64.html
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-- -----------------------------------------------------------------------
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--
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-- 6510 wrapper for 65xx core
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-- Adds 8 bit I/O port mapped at addresses $0000 to $0001
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--
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-- -----------------------------------------------------------------------
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library IEEE;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-- -----------------------------------------------------------------------
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entity cpu_6510 is
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generic (
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pipelineOpcode : boolean;
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pipelineAluMux : boolean;
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pipelineAluOut : boolean;
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| 214 | markw | emulate_bitfade : boolean;
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emulate_01_write : boolean
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| 1 | markw | );
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port (
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clk : in std_logic;
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ena_1khz : in std_logic := '0';
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enable : in std_logic;
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halt : in std_logic;
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reset : in std_logic;
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nmi_n : in std_logic;
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irq_n : in std_logic;
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we : out std_logic;
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a : out unsigned(15 downto 0);
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d : in unsigned(7 downto 0);
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q : out unsigned(7 downto 0);
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| 214 | markw | vic_last_data : in unsigned(7 downto 0) := (others => '1');
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| 1 | markw | diIO : in unsigned(7 downto 0);
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doIO : out unsigned(7 downto 0);
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debugOpcode : out unsigned(7 downto 0);
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| 214 | markw | debugJam : out std_logic;
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| 1 | markw | debugPc : out unsigned(15 downto 0);
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debugA : out unsigned(7 downto 0);
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debugX : out unsigned(7 downto 0);
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debugY : out unsigned(7 downto 0);
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debugS : out unsigned(7 downto 0);
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debug_flags : out unsigned(7 downto 0);
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debug_io : out unsigned(7 downto 0)
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);
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end cpu_6510;
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-- -----------------------------------------------------------------------
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architecture rtl of cpu_6510 is
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signal localA : unsigned(15 downto 0);
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signal localD : unsigned(7 downto 0);
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signal localQ : unsigned(7 downto 0);
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signal localWe : std_logic;
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signal currentIO : unsigned(7 downto 0);
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signal ioDir : unsigned(7 downto 0);
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signal ioData : unsigned(7 downto 0);
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| 214 | markw | signal accessing_IO : boolean;
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| 1 | markw | signal ioFade : unsigned(7 downto 0) := (others => '0');
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begin
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cpuInstance: entity work.cpu_65xx
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generic map (
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pipelineOpcode => pipelineOpcode,
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pipelineAluMux => pipelineAluMux,
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pipelineAluOut => pipelineAluOut
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)
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port map (
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clk => clk,
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enable => enable,
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halt => halt,
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reset => reset,
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nmi_n => nmi_n,
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irq_n => irq_n,
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d => localD,
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q => localQ,
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addr => localA,
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we => localWe,
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debugOpcode => debugOpcode,
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| 214 | markw | debugJam => debugJam,
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| 1 | markw | debugPc => debugPc,
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debugA => debugA,
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debugX => debugX,
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debugY => debugY,
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debugS => debugS,
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debug_flags => debug_flags
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);
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| 214 | markw | accessing_IO <= localA(15 downto 1) = 0;
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| 1 | markw | ||
| 214 | markw | process(d, localA, ioDir, currentIO, accessing_IO)
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| 1 | markw | begin
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localD <= d;
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| 214 | markw | if accessing_IO then
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| 1 | markw | if localA(0) = '0' then
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localD <= ioDir;
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else
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localD <= currentIO;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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| 214 | markw | if accessing_IO then
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| 1 | markw | if localWe = '1'
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and enable = '1' then
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if localA(0) = '0' then
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ioDir <= localQ;
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else
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ioData <= localQ;
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end if;
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end if;
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end if;
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if reset = '1' then
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ioDir <= (others => '0');
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end if;
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end if;
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end process;
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| 214 | markw | process(ioDir, ioData, diIO, ioFade)
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| 1 | markw | begin
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for i in 0 to 7 loop
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if ioDir(i) = '0' then
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currentIO(i) <= diIO(i);
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else
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currentIO(i) <= ioData(i);
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end if;
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end loop;
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if emulate_bitfade then
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currentIO(7) <= ioFade(7);
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currentIO(6) <= ioFade(6);
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currentIO(3) <= ioFade(3);
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end if;
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end process;
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-- Cunnect zee wires
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a <= localA;
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| 214 | markw | q <= vic_last_data when (emulate_01_write and accessing_IO) else localQ;
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| 1 | markw | we <= localWe;
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doIO <= currentIO;
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debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
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end architecture;
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