repo2/atari_chips/pokeyv2/sample/adpcm.vhdl @ 1476
| 1155 | markw | ---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY sample_adpcm IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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| 1167 | markw | SYNCRESET : IN STD_LOGIC_VECTOR(3 downto 0); -- reset accumulator/step for next update
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| 1159 | markw | ||
| 1167 | markw | select_channel : out std_logic_vector(1 downto 0); -- ask for current data for this channel
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store : OUT std_logic;
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data_out : OUT std_logic_vector(15 downto 0); -- current output
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dirty : IN STD_LOGIC_VECTOR(3 downto 0); -- channel needs updating
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data_request : out std_logic;
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data_ready : in std_logic;
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data_in : in std_logic_vector(3 downto 0);
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STEP_ADDR : out std_logic_vector(6 downto 0); -- ask for step value
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STEP_REQUEST : out std_logic;
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STEP_READY : in std_logic;
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| 1169 | markw | STEP_VALUE : in std_logic_vector(14 downto 0)
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| 1155 | markw | );
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END sample_adpcm;
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ARCHITECTURE vhdl OF sample_adpcm IS
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function stepadj_fn(x: std_logic_vector(2 downto 0)) return signed is
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begin
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case x is
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| 1164 | markw | when "000" => return to_signed(-1,5);
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when "001" => return to_signed(-1,5);
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when "010" => return to_signed(-1,5);
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when "011" => return to_signed(-1,5);
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when "100" => return to_signed(2,5);
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when "101" => return to_signed(4,5);
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when "110" => return to_signed(6,5);
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when "111" => return to_signed(8,5);
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| 1155 | markw | end case;
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end stepadj_fn;
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| 1163 | markw | signal acc0_reg : signed(15 downto 0);
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signal acc0_next : signed(15 downto 0);
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| 1155 | markw | ||
| 1163 | markw | signal acc1_reg : signed(15 downto 0);
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signal acc1_next : signed(15 downto 0);
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| 1155 | markw | ||
| 1163 | markw | signal acc2_reg : signed(15 downto 0);
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signal acc2_next : signed(15 downto 0);
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| 1155 | markw | ||
| 1163 | markw | signal acc3_reg : signed(15 downto 0);
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signal acc3_next : signed(15 downto 0);
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| 1155 | markw | ||
| 1163 | markw | signal acc_next : signed(15 downto 0);
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signal acc_mux : signed(15 downto 0);
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| 1155 | markw | ||
| 1164 | markw | signal decstep0_reg : unsigned(6 downto 0);
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signal decstep0_next : unsigned(6 downto 0);
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| 1155 | markw | ||
| 1164 | markw | signal decstep1_reg : unsigned(6 downto 0);
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signal decstep1_next : unsigned(6 downto 0);
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| 1155 | markw | ||
| 1164 | markw | signal decstep2_reg : unsigned(6 downto 0);
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signal decstep2_next : unsigned(6 downto 0);
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| 1155 | markw | ||
| 1164 | markw | signal decstep3_reg : unsigned(6 downto 0);
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signal decstep3_next : unsigned(6 downto 0);
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| 1155 | markw | ||
| 1164 | markw | signal decstep_next : unsigned(6 downto 0);
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signal decstep_mux : unsigned(6 downto 0);
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| 1155 | markw | ||
| 1158 | markw | signal write_ch0 : std_logic;
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signal write_ch1 : std_logic;
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signal write_ch2 : std_logic;
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signal write_ch3 : std_logic;
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| 1155 | markw | ||
| 1167 | markw | signal sel : std_logic_vector(1 downto 0);
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| 1159 | markw | ||
signal syncreset_next : std_logic_vector(3 downto 0);
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signal syncreset_reg : std_logic_vector(3 downto 0);
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| 1167 | markw | ||
signal dirty_reg : std_logic_vector(3 downto 0);
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signal dirty_next : std_logic_vector(3 downto 0);
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signal code_reg : std_logic_vector(3 downto 0);
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signal code_next : std_logic_vector(3 downto 0);
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| 1283 | markw | signal state_reg : std_logic_vector(2 downto 0);
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signal state_next: std_logic_vector(2 downto 0);
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constant state_ch0_mem_req : std_logic_vector(2 downto 0) := "000";
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constant state_ch0_step_req : std_logic_vector(2 downto 0) := "001";
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constant state_ch1_mem_req : std_logic_vector(2 downto 0) := "010";
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constant state_ch1_step_req : std_logic_vector(2 downto 0) := "011";
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constant state_ch2_mem_req : std_logic_vector(2 downto 0) := "100";
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constant state_ch2_step_req : std_logic_vector(2 downto 0) := "101";
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constant state_ch3_mem_req : std_logic_vector(2 downto 0) := "110";
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constant state_ch3_step_req : std_logic_vector(2 downto 0) := "111";
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| 1155 | markw | BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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acc0_reg <= (others=>'0');
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acc1_reg <= (others=>'0');
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acc2_reg <= (others=>'0');
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acc3_reg <= (others=>'0');
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decstep0_reg <= (others=>'0');
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decstep1_reg <= (others=>'0');
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decstep2_reg <= (others=>'0');
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decstep3_reg <= (others=>'0');
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| 1159 | markw | syncreset_reg <= (others=>'0');
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| 1167 | markw | dirty_reg <= (others=>'0');
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code_reg <= (others=>'0');
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state_reg <= state_ch0_mem_req;
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| 1155 | markw | elsif (clk'event and clk='1') then
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acc0_reg <= acc0_next;
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acc1_reg <= acc1_next;
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acc2_reg <= acc2_next;
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acc3_reg <= acc3_next;
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decstep0_reg <= decstep0_next;
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decstep1_reg <= decstep1_next;
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decstep2_reg <= decstep2_next;
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decstep3_reg <= decstep3_next;
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| 1159 | markw | syncreset_reg <= syncreset_next;
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| 1167 | markw | dirty_reg <= dirty_next;
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code_reg <= code_next;
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state_reg <= state_next;
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| 1155 | markw | end if;
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end process;
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| 1169 | markw | process(state_reg, dirty, dirty_reg, code_reg, data_in, data_ready, step_ready)
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| 1167 | markw | begin
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code_next <= code_reg;
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dirty_next <= dirty_reg or dirty;
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state_next <= state_reg;
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| 1174 | markw | data_request <= '0';
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| 1167 | markw | step_request <= '0';
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sel <= (others=>'0');
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write_ch0 <= '0';
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write_ch1 <= '0';
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write_ch2 <= '0';
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write_ch3 <= '0';
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store <= step_ready;
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if (data_ready='1') then
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code_next <= data_in;
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end if;
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case state_reg is
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when state_ch0_mem_req =>
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sel <= "00";
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data_request <= dirty_reg(0);
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if (data_ready='1') then
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code_next <= data_in;
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state_next <= state_ch0_step_req;
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end if;
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if (dirty_reg(0)='0') then
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state_next <= state_ch1_mem_req;
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end if;
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when state_ch0_step_req =>
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step_request <= '1';
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sel <= "00";
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write_ch0 <= step_ready;
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if (step_ready='1') then
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state_next <= state_ch1_mem_req;
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dirty_next(0) <= '0';
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end if;
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when state_ch1_mem_req =>
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sel <= "01";
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data_request <= dirty_reg(1);
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if (data_ready='1') then
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code_next <= data_in;
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state_next <= state_ch1_step_req;
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end if;
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if (dirty_reg(1)='0') then
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state_next <= state_ch2_mem_req;
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end if;
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when state_ch1_step_req =>
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step_request <= '1';
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sel <= "01";
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write_ch1 <= step_ready;
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if (step_ready='1') then
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state_next <= state_ch2_mem_req;
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dirty_next(1) <= '0';
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end if;
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when state_ch2_mem_req =>
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sel <= "10";
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data_request <= dirty_reg(2);
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if (data_ready='1') then
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code_next <= data_in;
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state_next <= state_ch2_step_req;
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end if;
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if (dirty_reg(2)='0') then
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state_next <= state_ch3_mem_req;
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end if;
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when state_ch2_step_req =>
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step_request <= '1';
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sel <= "10";
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write_ch2 <= step_ready;
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if (step_ready='1') then
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state_next <= state_ch3_mem_req;
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dirty_next(2) <= '0';
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end if;
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when state_ch3_mem_req =>
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sel <= "11";
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data_request <= dirty_reg(3);
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if (data_ready='1') then
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code_next <= data_in;
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state_next <= state_ch3_step_req;
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end if;
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if (dirty_reg(3)='0') then
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state_next <= state_ch0_mem_req;
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end if;
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when state_ch3_step_req =>
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step_request <= '1';
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sel <= "11";
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write_ch3 <= step_ready;
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if (step_ready='1') then
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state_next <= state_ch0_mem_req;
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dirty_next(3) <= '0';
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end if;
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when others =>
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state_next <= state_ch0_mem_req;
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end case;
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end process;
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| 1155 | markw | process(acc0_reg, acc1_reg, acc2_reg, acc3_reg,
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decstep0_reg, decstep1_reg, decstep2_reg, decstep3_reg,
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| 1158 | markw | acc_next, decstep_next,
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write_ch0,write_ch1,write_ch2,write_ch3)
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| 1155 | markw | begin
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acc0_next <= acc0_reg;
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acc1_next <= acc1_reg;
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acc2_next <= acc2_reg;
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acc3_next <= acc3_reg;
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decstep0_next <= decstep0_reg;
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decstep1_next <= decstep1_reg;
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decstep2_next <= decstep2_reg;
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decstep3_next <= decstep3_reg;
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| 1158 | markw | ||
if (write_ch0='1') then
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acc0_next <= acc_next;
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decstep0_next <= decstep_next;
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end if;
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if (write_ch1='1') then
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acc1_next <= acc_next;
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decstep1_next <= decstep_next;
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end if;
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| 1155 | markw | ||
| 1158 | markw | if (write_ch2='1') then
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acc2_next <= acc_next;
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decstep2_next <= decstep_next;
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end if;
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if (write_ch3='1') then
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acc3_next <= acc_next;
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decstep3_next <= decstep_next;
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end if;
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| 1155 | markw | end process;
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| 1167 | markw | process(sel,syncreset_reg, syncreset, step_ready,
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| 1155 | markw | acc0_reg, acc1_reg, acc2_reg, acc3_reg,
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| 1167 | markw | decstep0_reg, decstep1_reg, decstep2_reg, decstep3_reg
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| 1155 | markw | )
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| 1171 | markw | variable rst : std_logic;
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| 1155 | markw | begin
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acc_mux <= (others=>'0');
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decstep_mux <= (others=>'0');
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| 1159 | markw | ||
| 1167 | markw | syncreset_next <= (syncreset or syncreset_reg);
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| 1171 | markw | ||
rst := '0';
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| 1159 | markw | ||
| 1158 | markw | case sel is
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| 1167 | markw | when "00" =>
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| 1155 | markw | acc_mux <= acc0_reg;
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decstep_mux <= decstep0_reg;
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| 1171 | markw | rst := syncreset_reg(0) or syncreset(0);
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| 1167 | markw | syncreset_next(0) <= (syncreset_reg(0) or syncreset(0)) and not(step_ready);
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when "01" =>
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| 1155 | markw | acc_mux <= acc1_reg;
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decstep_mux <= decstep1_reg;
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| 1171 | markw | rst := syncreset_reg(1) or syncreset(1);
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| 1167 | markw | syncreset_next(1) <= (syncreset_reg(1) or syncreset(1)) and not(step_ready);
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when "10" =>
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| 1155 | markw | acc_mux <= acc2_reg;
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| 1171 | markw | decstep_mux <= decstep2_reg;
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rst := syncreset_reg(2) or syncreset(2);
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| 1167 | markw | syncreset_next(2) <= (syncreset_reg(2) or syncreset(2)) and not(step_ready);
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when "11" =>
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| 1155 | markw | acc_mux <= acc3_reg;
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decstep_mux <= decstep3_reg;
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| 1171 | markw | rst := syncreset_reg(3) or syncreset(3);
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| 1167 | markw | syncreset_next(3) <= (syncreset_reg(3) or syncreset(3)) and not(step_ready);
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| 1155 | markw | when others =>
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end case;
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| 1158 | markw | ||
| 1171 | markw | if (rst='1') then
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| 1158 | markw | acc_mux <= (others=>'0');
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decstep_mux <= (others=>'0');
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end if;
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| 1155 | markw | end process;
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| 1158 | markw | process(acc_mux,decstep_mux,
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| 1167 | markw | code_reg, step_value)
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| 1155 | markw | ||
variable code : std_logic_vector(3 downto 0);
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variable codeadj : signed(8 downto 0);
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| 1160 | markw | variable stepsize : signed(17 downto 0);
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variable vlue : signed(26 downto 0);
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| 1166 | markw | variable vlue8 : signed(16 downto 0);
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| 1164 | markw | variable decstepnext : signed(7 downto 0);
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| 1165 | markw | variable acc_sum : signed(16 downto 0);
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variable oflow : boolean;
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| 1155 | markw | begin
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| 1156 | markw | acc_next <= acc_mux;
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decstep_next <= decstep_mux;
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| 1158 | markw | ||
codeadj:= (others=>'0');
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| 1164 | markw | ||
| 1167 | markw | codeadj := resize(signed('0'&code_reg(2 downto 0)),8)&"1";
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| 1158 | markw | ||
| 1167 | markw | stepsize := resize(signed('0'&step_value),18);
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| 1155 | markw | ||
| 1158 | markw | vlue :=codeadj*stepsize;
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| 1166 | markw | ||
| 1167 | markw | if (code_reg(3)='0') then
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| 1166 | markw | vlue8 := vlue(19 downto 3);
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else
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vlue8 := -vlue(19 downto 3);
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end if;
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acc_sum := resize(acc_mux,17) + vlue8;
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| 1165 | markw | oflow := acc_sum(16)/=acc_sum(15);
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if (oflow) then
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acc_next <= resize(acc_sum(16 downto 16),16);
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else
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acc_next <= acc_sum(15 downto 0);
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end if;
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| 1155 | markw | ||
| 1167 | markw | decstepnext := resize(stepadj_fn(code_reg(2 downto 0)),8) + signed(resize(decstep_mux,8));
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| 1164 | markw | if (decstepnext>88) then
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decstepnext := to_signed(88,8);
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| 1158 | markw | elsif (decstepnext<0) then
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| 1164 | markw | decstepnext := to_signed(0,8);
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| 1155 | markw | end if;
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| 1164 | markw | decstep_next <= unsigned(decstepnext(6 downto 0));
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| 1155 | markw | end process;
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| 1163 | markw | data_out(15) <= not(acc_mux(15));
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data_out(14 downto 0) <= std_logic_vector(acc_mux(14 downto 0));
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| 1167 | markw | ||
select_channel <= sel;
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step_addr <= std_logic_vector(decstep_mux);
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| 1155 | markw | ||
end vhdl;
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