repo2/atari_chips/pokeyv2/pllv3.cmp @ 1476
| 1422 | markw | --Copyright (C) 2024 Intel Corporation. All rights reserved.
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| 1312 | markw | --Your use of Intel Corporation's design tools, logic functions
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--and other software and tools, and any partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Intel Program License
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--Subscription Agreement, the Intel Quartus Prime License Agreement,
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--the Intel FPGA IP License Agreement, or other applicable license
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--agreement, including, without limitation, that your use is for
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--the sole purpose of programming logic devices manufactured by
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--Intel and sold by Intel or its authorized distributors. Please
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--refer to the applicable agreement for further details, at
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--https://fpgasoftware.intel.com/eula.
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component pllv3
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PORT
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(
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inclk0 : IN STD_LOGIC := '0';
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c0 : OUT STD_LOGIC ;
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c1 : OUT STD_LOGIC ;
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c2 : OUT STD_LOGIC ;
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c3 : OUT STD_LOGIC ;
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locked : OUT STD_LOGIC
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);
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end component;
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