repo2/atari_chips/pokeyv2/PSG/envelope.vhdl @ 1476
| 1031 | markw | ---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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| 1036 | markw | ENTITY PSG_envelope IS
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| 1031 | markw | PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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| 1038 | markw | ||
STEP32 : IN STD_LOGIC;
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| 1031 | markw | COUNT_RESET : IN STD_LOGIC;
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SHAPE : IN STD_LOGIC_VECTOR(3 downto 0);
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PERIOD : IN STD_LOGIC_VECTOR(15 downto 0);
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| 1038 | markw | ENVELOPE : OUT STD_LOGIC_VECTOR(4 downto 0)
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| 1031 | markw | );
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| 1036 | markw | END PSG_envelope;
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| 1031 | markw | ||
| 1036 | markw | ARCHITECTURE vhdl OF PSG_envelope IS
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| 1038 | markw | signal envelope_reg: std_logic_vector(4 downto 0);
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signal envelope_next: std_logic_vector(4 downto 0);
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| 1031 | markw | ||
| 1038 | markw | signal count_reg: unsigned(5 downto 0);
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signal count_next: unsigned(5 downto 0);
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| 1032 | markw | ||
| 1031 | markw | signal envelope_tick: std_logic;
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BEGIN
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| 1038 | markw | -- register
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process(clk, reset_n)
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begin
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if (reset_n = '0') then
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count_reg <= (others=>'0');
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envelope_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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count_reg <= count_next;
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envelope_reg <= envelope_next;
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end if;
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end process;
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envelope_ticker : entity work.PSG_freqdiv
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GENERIC MAP
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(
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bits => 16
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)
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PORT MAP
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(
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CLK => clk,
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RESET_N => reset_n,
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ENABLE => enable,
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| 1047 | markw | ||
SYNC_RESET => count_reset,
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| 1031 | markw | ||
| 1038 | markw | BIT_OUT => envelope_tick,
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THRESHOLD => unsigned(PERIOD)
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);
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-- next state
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| 1064 | markw | process(count_reg,shape,envelope_reg,envelope_tick,count_reset)
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| 1038 | markw | variable continue : std_logic;
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variable attack : std_logic;
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variable alternate : std_logic;
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variable hold : std_logic;
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variable tmprep : std_logic_vector(4 downto 0);
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begin
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count_next <= count_reg;
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envelope_next <= envelope_reg;
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continue := shape(3);
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attack := shape(2);
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alternate := shape(1);
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hold := shape(0);
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if (count_reset='1') then
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count_next <= (others=>'0');
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else
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if (envelope_tick='1') then
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count_next <= count_reg+1;
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if ((hold and count_reg(5))='1') then
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envelope_next <= (others=>alternate xor attack);
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else
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tmprep := (others=>(count_reg(5) and alternate) xnor attack);
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envelope_next <= std_logic_vector(count_reg(4 downto 0)) xor tmprep;
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end if;
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if (((hold or not(continue)) and count_reg(5))='1') then
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if (continue='0') then
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envelope_next <= (others=>'0');
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end if;
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count_next(5) <= '1';
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end if;
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end if;
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end if;
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end process;
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-- output
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envelope <= envelope_reg(4 downto 1)&(envelope_reg(0) and STEP32);
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| 1031 | markw | END vhdl;
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