repo2/atari_chips/pokey/pokey_mixer.vhdl @ 1476
| 714 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY pokey_mixer IS
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PORT
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(
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CLK : IN STD_LOGIC;
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| 734 | markw | SUM : IN STD_LOGIC_VECTOR(6 downto 0); -- unsigned
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| 714 | markw | ||
VOLUME_OUT_NEXT : OUT STD_LOGIC_vector(15 downto 0)
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);
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END pokey_mixer;
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ARCHITECTURE vhdl OF pokey_mixer IS
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signal volume_next : std_logic_vector(15 downto 0);
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signal y1 : signed(15 downto 0);
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signal y1_reg : signed(15 downto 0);
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signal y2 : signed(15 downto 0);
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signal ych : signed(15 downto 0);
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signal yadj_next : signed(31 downto 0);
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signal yadj_reg : signed(31 downto 0);
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signal b_in : signed(15 downto 0);
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BEGIN
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process(clk)
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begin
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if (clk'event and clk='1') then
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YADJ_REG <= YADJ_NEXT;
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Y1_REG <= Y1;
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END IF;
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END PROCESS;
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-- next state
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| 734 | markw | process (sum, y1, y2, y1_reg, yadj_reg)
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| 714 | markw | type LOOKUP_TYPE is array (0 to 32) of signed(15 downto 0);
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variable lookup : LOOKUP_TYPE;
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begin
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-- replace with piecewise interp. Takes a mul unit but saves lookup space.
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lookup := (x"86E8" ,x"9E40" ,x"B3E3" ,x"C7E3" ,x"DA52" ,x"EB42" ,x"FAC5" ,x"08ED" ,x"15CB" ,x"2172" ,x"2BF4" ,x"3562" ,x"3DCE" ,x"454B" ,x"4BEA" ,x"51BD" ,x"56D6" ,x"5B47" ,x"5F22" ,x"6278" ,x"655C" ,x"67E0" ,x"6A15" ,x"6C0D" ,x"6DDB" ,x"6F90" ,x"713E" ,x"72F7" ,x"74CD" ,x"76D2" ,x"7918" ,x"7BB0" ,x"7EAD");
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| 734 | markw | y1 <= lookup(to_integer(unsigned(sum(5 downto 1))));
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y2 <= lookup(to_integer(unsigned(sum(5 downto 1)))+1);
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| 714 | markw | ||
ych <= y2-y1;
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volume_next <= std_logic_vector(yadj_reg(20 downto 5) + y1_reg);
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--case volume_sum(9 downto 0) is
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--end case;
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end process;
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| 734 | markw | B_in <= signed("00000000000"&sum(0 downto 0)&"0000");
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| 714 | markw | linterp_mult : entity work.mult_infer
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PORT MAP( A => signed(ych),
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B => b_in,
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RESULT => yadj_next);
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-- output
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volume_out_next <= volume_next;
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END vhdl;
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