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//
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// data_io.v
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//
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// data_io for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2015-2017 Sorgelig
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// Copyright (c) 2019 György Szombathelyi
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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///////////////////////////////////////////////////////////////////////
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module data_io
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(
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// Global clock. It should be around 100MHz (higher is better).
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input clk_sys,
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// Global SPI clock from ARM. 24MHz
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input SPI_SCK,
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input SPI_SS2,
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input SPI_DI,
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// ARM -> FPGA download
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input ioctl_wait,
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output reg ioctl_download = 0, // signal indicating an active download
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output reg [7:0] ioctl_index, // menu index used to upload the file
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output reg ioctl_wr = 0,
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output reg [24:0] ioctl_addr,
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output reg [15:0] ioctl_dout
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);
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/////////////////////////////// DOWNLOADING ///////////////////////////////
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localparam UIO_FILE_TX = 8'h53;
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localparam UIO_FILE_TX_DAT = 8'h54;
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localparam UIO_FILE_INDEX = 8'h55;
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// SPI receiver IO -> FPGA
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reg spi_receiver_strobe_r = 0;
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reg spi_transfer_end_r = 1;
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reg [7:0] spi_byte_in;
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// data_io has its own SPI interface to the io controller
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// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys
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always@(posedge SPI_SCK or posedge SPI_SS2) begin
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reg [6:0] sbuf;
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reg [2:0] bit_cnt;
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if(SPI_SS2) begin
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spi_transfer_end_r <= 1;
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bit_cnt <= 0;
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end else begin
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spi_transfer_end_r <= 0;
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bit_cnt <= bit_cnt + 1'd1;
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if(bit_cnt != 7)
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sbuf[6:0] <= { sbuf[5:0], SPI_DI };
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// finished reading a byte, prepare to transfer to clk_sys
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if(bit_cnt == 7) begin
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spi_byte_in <= { sbuf, SPI_DI};
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spi_receiver_strobe_r <= ~spi_receiver_strobe_r;
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end
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end
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end
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always @(posedge clk_sys) begin
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reg spi_receiver_strobe;
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reg spi_transfer_end;
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reg spi_receiver_strobeD;
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reg spi_transfer_endD;
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reg [7:0] acmd;
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reg [2:0] abyte_cnt; // counts bytes
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reg [24:0] addr;
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reg wr_int;
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reg clkrefD;
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reg hi;
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//synchronize between SPI and sys clock domains
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spi_receiver_strobeD <= spi_receiver_strobe_r;
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spi_receiver_strobe <= spi_receiver_strobeD;
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spi_transfer_endD <= spi_transfer_end_r;
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spi_transfer_end <= spi_transfer_endD;
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if (~spi_transfer_endD & spi_transfer_end) begin
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abyte_cnt <= 3'd0;
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end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin
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if(~&abyte_cnt) abyte_cnt <= abyte_cnt + 1'd1;
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if(abyte_cnt == 0) begin
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acmd <= spi_byte_in;
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hi <= 0;
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end else begin
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case (acmd)
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UIO_FILE_TX: begin
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// prepare
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if(spi_byte_in) begin
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addr <= 25'h804000;
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ioctl_download <= 1;
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end else begin
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ioctl_addr <= addr;
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ioctl_download <= 0;
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end
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end
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// transfer
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UIO_FILE_TX_DAT: begin
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ioctl_addr <= addr;
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if (hi) ioctl_dout[15:8] <= spi_byte_in; else ioctl_dout[7:0] <= spi_byte_in;
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hi <= ~hi;
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if (hi) wr_int <= 1;
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end
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// expose file (menu) index
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UIO_FILE_INDEX: ioctl_index <= spi_byte_in;
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endcase
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end
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end
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ioctl_wr <= 0;
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if (wr_int & ~ioctl_wait) begin
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addr <= addr + 2'd2;
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ioctl_wr <= 1;
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wr_int <= 0;
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end
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end
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endmodule
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