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---------------------------------------------------------------------------
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-- (c) 2019 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.std_logic_misc.all;
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LIBRARY work;
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ENTITY switch_pal_ntsc IS
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GENERIC
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(
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CLOCKS : integer :=1;
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SYNC_ON : integer -- Which clock to send reset_n_out on and pll enable
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);
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PORT
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(
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RECONFIG_CLK : IN STD_LOGIC; -- A clock from another PLL
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RESET_N : IN STD_LOGIC;
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PAL : IN STD_LOGIC;
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SWITCH_ENA : in STD_LOGIC;
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INPUT_CLK : IN STD_LOGIC;
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PLL_CLKS : OUT STD_LOGIC_VECTOR(CLOCKS-1 downto 0);
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RESET_N_OUT : OUT STD_LOGIC
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);
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END switch_pal_ntsc;
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ARCHITECTURE vhdl OF switch_pal_ntsc IS
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-- pal/ntsc switches
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signal pll_reconfig_areset : std_logic;
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signal pll_reconfig_configupdate : std_logic;
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signal pll_reconfig_scanclk : std_logic;
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signal pll_reconfig_scanclkena : std_logic;
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signal pll_reconfig_scandata : std_logic;
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signal pll_reconfig_scandataout : std_logic;
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signal pll_reconfig_scandone : std_logic;
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signal pll_reconfig_busy : std_logic;
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signal pll_reconfig_rom_address : std_logic_vector(7 downto 0);
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signal pll_reconfig_rom_q : std_logic;
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signal q_reconfig_pal : std_logic_vector(7 downto 0);
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signal q_reconfig_ntsc : std_logic_vector(7 downto 0);
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signal pll_reconfig_write_rom_ena : std_logic;
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signal pll_reconfig_write_from_rom : std_logic;
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signal pll_reconfig_write_from_rom_next : std_logic;
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signal pll_pause_counter_reg : std_logic_vector(29 downto 0);
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signal pll_pause_counter_next : std_logic_vector(29 downto 0);
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signal pll_enable_reg : std_logic;
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signal pll_enable_next : std_logic;
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signal pll_enable_reg_sync : std_logic;
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signal pll_state_reg : std_logic_vector(3 downto 0);
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signal pll_state_next : std_logic_vector(3 downto 0);
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constant PLL_STATE_WAIT : std_logic_vector(3 downto 0) := "0000";
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constant PLL_STATE_WAIT_RECONF_ROM : std_logic_vector(3 downto 0) := "0001";
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constant PLL_STATE_RECONF_ROM : std_logic_vector(3 downto 0) := "0010";
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constant PLL_STATE_DISABLE : std_logic_vector(3 downto 0) := "0011";
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constant PLL_STATE_DISABLE_WAIT1 : std_logic_vector(3 downto 0) := "0100";
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constant PLL_STATE_DISABLE_WAIT2 : std_logic_vector(3 downto 0) := "0101";
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constant PLL_STATE_DISABLE_WAIT3 : std_logic_vector(3 downto 0) := "0110";
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constant PLL_STATE_DISABLE_WAIT4 : std_logic_vector(3 downto 0) := "0111";
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constant PLL_STATE_RECONFIG1 : std_logic_vector(3 downto 0) := "1000";
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constant PLL_STATE_RECONFIG1_WAIT_CONFIG : std_logic_vector(3 downto 0) := "1001";
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constant PLL_STATE_RECONFIG1_WAIT_LOCK : std_logic_vector(3 downto 0) := "1010";
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constant PLL_STATE_PAUSE1 : std_logic_vector(3 downto 0) := "1011";
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signal pll_trigger_reconfig : std_logic;
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signal pll_upstream_reset : std_logic;
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signal pll_upstream_reset_pal : std_logic;
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signal pll_upstream_reset_ntsc : std_logic;
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signal pll_downstream_reset : std_logic;
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signal reset_n_next : std_logic;
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signal reset_n_reg : std_logic;
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signal reset_n_reg_sync : std_logic;
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signal CLK_PLL1 : std_logic;
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signal PLL_LOCKED1 : std_logic;
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signal PLL_LOCKED : std_logic;
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signal CLK_RAW : std_logic_vector(5 downto 0);
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signal pal_fpga_sync : std_logic;
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signal reconfig_to_pal_reg : std_logic;
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signal reconfig_to_pal_next : std_logic;
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BEGIN
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generic_pll : entity work.pll_pal
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PORT MAP(inclk0 => INPUT_CLK,
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c0 => CLK_PLL1,
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locked => PLL_LOCKED1,
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areset => pll_reconfig_areset,
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-- from reconfig
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configupdate => pll_reconfig_configupdate,
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scanclk => pll_reconfig_scanclk,
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scanclkena => pll_reconfig_scanclkena,
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scandata => pll_reconfig_scandata,
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-- back to reconfig
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scandataout => pll_reconfig_scandataout,
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scandone => pll_reconfig_scandone
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);
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generic_pll2 : entity work.pll_downstream_pal
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PORT MAP(inclk0 => CLK_PLL1,
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c0 => CLK_RAW(0),
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c1 => CLK_RAW(1),
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c2 => CLK_RAW(2),
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c3 => CLK_RAW(3),
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--c4 => CLK_RAW(4),
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areset => pll_downstream_reset,
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locked => PLL_LOCKED
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);
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generic_pll1_reconfig : entity work.video_pll_reconfig
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PORT MAP
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(
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busy => pll_reconfig_busy,
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clock => RECONFIG_CLK,
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counter_param => (OTHERS => '0'),
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counter_type => (OTHERS => '0'),
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data_in => (OTHERS => '0'),
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read_param => '0',
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write_param => '0',
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--data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
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pll_areset => pll_reconfig_areset,
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pll_areset_in => pll_upstream_reset,
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pll_configupdate => pll_reconfig_configupdate,
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pll_scanclk => pll_reconfig_scanclk,
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pll_scanclkena => pll_reconfig_scanclkena,
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pll_scandata => pll_reconfig_scandata,
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pll_scandataout => pll_reconfig_scandataout,
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pll_scandone => pll_reconfig_scandone,
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reset_rom_address => '0',
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rom_address_out => pll_reconfig_rom_address,
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rom_data_in => pll_reconfig_rom_q,
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write_from_rom => pll_reconfig_write_from_rom,
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write_rom_ena => pll_reconfig_write_rom_ena,
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reconfig => pll_trigger_reconfig,
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reset => not(RESET_N)
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);
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pll_rom_pal : entity work.pal_rom
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port map(
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address => pll_reconfig_rom_address,
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clock => RECONFIG_CLK,
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rden => pll_reconfig_write_rom_ena,
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q => q_reconfig_pal
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);
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pll_rom_ntsc : entity work.ntsc_rom
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port map(
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address => pll_reconfig_rom_address,
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clock => RECONFIG_CLK,
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rden => pll_reconfig_write_rom_ena,
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q => q_reconfig_ntsc
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);
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pll_reconfig_rom_q <= q_reconfig_pal(0) when reconfig_to_pal_reg = '1' else q_reconfig_ntsc(0);
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process(RECONFIG_CLK,RESET_N)
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begin
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if (RESET_N='0') then
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pll_state_reg <= PLL_STATE_WAIT;
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pll_pause_counter_reg<= (others=>'0');
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pll_enable_reg<='0';
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pll_reconfig_write_from_rom <= '0';
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reset_n_reg <= '0';
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reconfig_to_pal_reg <= '1';
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elsif (RECONFIG_CLK'event and RECONFIG_CLK='1') then
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pll_state_reg <= pll_state_next;
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pll_pause_counter_reg <= pll_pause_counter_next;
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pll_enable_reg <= pll_enable_next;
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pll_reconfig_write_from_rom <= pll_reconfig_write_from_rom_next;
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reset_n_reg <= reset_n_next;
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reconfig_to_pal_reg <= reconfig_to_pal_next;
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end if;
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end process;
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pal_synchronizer : entity work.synchronizer
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port map (clk=>RECONFIG_CLK, raw=>pal, sync=>pal_fpga_sync);
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process (pll_state_reg, pal_fpga_sync, pll_pause_counter_reg,pll_enable_reg, PLL_LOCKED1, PLL_LOCKED, pll_reconfig_busy,reconfig_to_pal_reg)
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begin
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pll_reconfig_write_from_rom_next <= '0';
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pll_state_next <= pll_state_reg;
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reset_n_next <= '1';
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reconfig_to_pal_next <= reconfig_to_pal_reg;
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pll_pause_counter_next <= std_logic_vector(unsigned(pll_pause_counter_reg)+1);
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pll_trigger_reconfig <= '0';
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pll_downstream_reset <= '0';
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pll_upstream_reset <= '0';
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pll_enable_next <= pll_enable_reg;
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case pll_state_reg is
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when PLL_STATE_WAIT =>
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pll_enable_next <= '1';
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if SWITCH_ENA = '1' then
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reset_n_next <= PLL_LOCKED;
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if (not(pal_fpga_sync = reconfig_to_pal_reg) and PLL_LOCKED='1' and PLL_LOCKED1='1') then
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reconfig_to_pal_next <= pal_fpga_sync;
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pll_state_next <= PLL_STATE_WAIT_RECONF_ROM;
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pll_reconfig_write_from_rom_next <= '1';
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end if;
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end if;
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when PLL_STATE_WAIT_RECONF_ROM =>
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pll_state_next <= PLL_STATE_RECONF_ROM;
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when PLL_STATE_RECONF_ROM =>
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if (pll_reconfig_busy = '0') then
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pll_state_next <= PLL_STATE_DISABLE;
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pll_pause_counter_next <= (others=>'0');
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end if;
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when PLL_STATE_DISABLE =>
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if (pll_pause_counter_reg(16)='1') then
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pll_enable_next <= '0';
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pll_state_next <= PLL_STATE_DISABLE_WAIT1;
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end if;
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-- Wait for pll_enable_next to make through synchronizer
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when PLL_STATE_DISABLE_WAIT1 =>
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pll_state_next <= PLL_STATE_DISABLE_WAIT2;
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when PLL_STATE_DISABLE_WAIT2 =>
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pll_state_next <= PLL_STATE_DISABLE_WAIT3;
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when PLL_STATE_DISABLE_WAIT3 =>
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pll_state_next <= PLL_STATE_DISABLE_WAIT4;
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when PLL_STATE_DISABLE_WAIT4 =>
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pll_state_next <= PLL_STATE_RECONFIG1;
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-- Set params for upstream pll and reset downstream pll
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when PLL_STATE_RECONFIG1 =>
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pll_trigger_reconfig <= '1';
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pll_downstream_reset <= '1';
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pll_state_next <= PLL_STATE_RECONFIG1_WAIT_CONFIG;
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when PLL_STATE_RECONFIG1_WAIT_CONFIG =>
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--pll_downstream_reset <= '1';
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if (pll_reconfig_busy = '0') then
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pll_state_next <= PLL_STATE_RECONFIG1_WAIT_LOCK;
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end if;
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when PLL_STATE_RECONFIG1_WAIT_LOCK =>
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--pll_downstream_reset <= '1';
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if (PLL_LOCKED1 = '1') then
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pll_state_next <= PLL_STATE_PAUSE1;
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pll_pause_counter_next <= (others=>'0');
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--pll_downstream_reset <= '0';
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end if;
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when PLL_STATE_PAUSE1 =>
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if (pll_pause_counter_reg(16)='1') then
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pll_state_next <= PLL_STATE_WAIT;
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end if;
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when others =>
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pll_state_next <= PLL_STATE_WAIT;
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end case;
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end process;
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reset_n_out <= reset_n_reg_sync;
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reset_synchronizer : entity work.synchronizer
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port map (clk=>CLK_RAW(SYNC_ON), raw=>reset_n_reg, sync=>reset_n_reg_sync);
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pll_enable_synchronizer : entity work.synchronizer
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port map (clk=>CLK_RAW(SYNC_ON), raw=>pll_enable_reg, sync=>pll_enable_reg_sync);
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GEN_CLKCTRL:
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for I in 0 to (CLOCKS-1) generate
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CLKCTRLX : entity work.clkctrl
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port map (
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inclk => CLK_RAW(I),
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ena => pll_enable_reg_sync,
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outclk => PLL_CLKS(I)
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);
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end generate GEN_CLKCTRL;
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end vhdl;
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