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## Generated SDC file "hello_led.out.sdc"
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## Copyright (C) 1991-2011 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
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## DATE "Fri Jul 06 23:05:47 2012"
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##
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## DEVICE "EP3C25Q240C8"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name clk_27 -period 37.037 [get_ports {CLOCK_27[0]}]
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create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
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set sdram_clk "pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]"
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set mem_clk "pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]"
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set sys_clk "pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]"
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty;
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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# SDRAM is clocked from sd1clk_pin, but the SDRAM controller uses memclk
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set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -max 6.4 [get_ports SDRAM_DQ[*]]
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set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -min 3.2 [get_ports SDRAM_DQ[*]]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports SDRAM_CLK] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks $sys_clk] -max 0 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks $sys_clk] -min -5 [get_ports {VGA_*}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_switcher|*}]
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set_clock_groups -asynchronous -group [get_clocks {clk_27}] -group [get_clocks {pll_switcher|*}]
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set_clock_groups -asynchronous -group [get_clocks {reconfig_pll|*}] -group [get_clocks {pll_switcher|*}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -to [get_ports {UART_TX}]
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set_false_path -to [get_ports {AUDIO_L}]
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set_false_path -to [get_ports {AUDIO_R}]
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set_false_path -to [get_ports {LED}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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set_multicycle_path -to {VGA_*[*]} -setup 2
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set_multicycle_path -to {VGA_*[*]} -hold 1
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set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $mem_clk] -setup 2
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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