EclaireXL

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, the Altera Quartus Prime License Agreement,

# the Altera MegaCore Function License Agreement, or other

# applicable license agreement, including, without limitation,

# that your use is for the sole purpose of programming logic

# devices manufactured by Altera and sold by Altera or its

# authorized distributors. Please refer to the applicable

# agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus Prime

# Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition

# Date created = 08:06:31 April 05, 2016

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

# veronica_assignment_defaults.qdf

# If this file doesn't exist, see file:

# assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

# file is updated automatically by the Quartus Prime software

# and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "MAX 10"

set_global_assignment -name DEVICE 10M08SAE144C8G

set_global_assignment -name TOP_LEVEL_ENTITY veronica

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:06:31 APRIL 05, 2016"

set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON

set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"

set_global_assignment -name VERILOG_FILE BCDMath.v

set_global_assignment -name VHDL_FILE veronica.vhd

set_global_assignment -name VERILOG_FILE FT816.v

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

set_global_assignment -name QIP_FILE pll_veronica.qip