repo2/ultimate_cart/veronica/store.v @ 1475
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// __
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// \\__/ o\ (C) 2013, 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Memory store states
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// The store states work for 8, 16 or 32 bit mode
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// ============================================================================
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//
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// Stores always write through to memory, then optionally update the cache if
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// there was a write hit.
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STORE1:
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begin
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case(store_what)
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`STW_ACC8: data_write(acc[7:0]);
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`STW_X8: data_write(x[7:0]);
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`STW_Y8: data_write(y[7:0]);
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`STW_Z8: data_write(8'h00);
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`STW_PC2316: data_write(pc[23:16]);
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`STW_PC158: data_write(pc[15:8]);
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`STW_PC70: data_write(pc[7:0]);
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`STW_SR70: data_write(sr8);
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`STW_DEF8: data_write(wdat);
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`STW_DEF70: begin data_write(wdat); mlb <= 1'b1; end
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`STW_DEF158: data_write(wdat[15:8]);
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`STW_DEF2316: data_write(wdat[23:16]);
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`STW_ACC70: begin data_write(acc); mlb <= 1'b1; end
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`STW_ACC158: data_write(acc[15:8]);
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`STW_X70: begin data_write(x); mlb <= 1'b1; end
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`STW_X158: data_write(x[15:8]);
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`STW_Y70: begin data_write(y); mlb <= 1'b1; end
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`STW_Y158: data_write(y[15:8]);
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`STW_Z70: begin data_write(8'h00); mlb <= 1'b1; end
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`STW_Z158: data_write(8'h00);
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`STW_DBR: data_write(dbr);
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`STW_DPR158: begin data_write(dpr[15:8]); mlb<= 1'b1; end
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`STW_DPR70: data_write(dpr);
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`STW_TMP158: begin data_write(tmp16[15:8]); mlb <= 1'b1; end
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`STW_TMP70: data_write(tmp16);
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`STW_IA158: begin data_write(ia[15:8]); mlb <= 1'b1; end
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`STW_IA70: data_write(ia);
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default: data_write(wdat);
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endcase
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`ifdef SUPPORT_DCACHE
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radr <= wadr; // Do a cache read to test the hit
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`endif
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state <= STORE2;
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end
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// Terminal state for stores. Update the data cache if there was a cache hit.
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// Clear any previously set lock status
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STORE2:
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if (rdy) begin
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// wdat <= dat_o;
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mlb <= 1'b0;
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data_nack();
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if (!em && (isMove|isSts)) begin
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state <= MVN3;
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retstate <= MVN3;
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end
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else begin
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if (em) begin
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if (isMove) begin
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state <= MVN816;
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retstate <= MVN816;
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end
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else begin
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moveto_ifetch();
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retstate <= IFETCH1;
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end
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end
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else begin
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moveto_ifetch();
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retstate <= IFETCH1;
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end
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end
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case(store_what)
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`STW_DEF70:
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begin
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wadr <= wadr + 24'd1;
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store_what <= `STW_DEF158;
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retstate <= STORE1;
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if ((b16[15:8]!=wdat[15:8]) || !STORE_SKIPPING || isTribyte) begin
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mlb <= 1'b1;
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vpa <= `FALSE; // override moveto_ifetch() setting.
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vda <= `FALSE;
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state <= STORE1;
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end
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end
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`STW_DEF158:
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if (isTribyte) begin
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mlb <= 1'b1;
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wadr <= wadr + 24'd1;
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vpa <= `FALSE; // override moveto_ifetch() setting.
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vda <= `FALSE;
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store_what <= `STW_DEF2316;
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state <= STORE1;
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end
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`STW_ACC70:
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begin
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mlb <= 1'b1;
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wadr <= wadr + 24'd1;
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_ACC158;
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state <= STORE1;
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end
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`STW_X70:
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begin
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mlb <= 1'b1;
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wadr <= wadr + 24'd1;
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_X158;
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state <= STORE1;
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end
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`STW_Y70:
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begin
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mlb <= 1'b1;
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wadr <= wadr + 24'd1;
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_Y158;
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state <= STORE1;
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end
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`STW_Z70:
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begin
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mlb <= 1'b1;
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wadr <= wadr + 24'd1;
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_Z158;
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state <= STORE1;
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end
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`STW_DPR158:
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begin
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set_sp();
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_DPR70;
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state <= STORE1;
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end
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`STW_TMP158:
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begin
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set_sp();
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_TMP70;
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state <= STORE1;
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end
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`STW_IA158:
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begin
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set_sp();
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_IA70;
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state <= STORE1;
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end
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`STW_PC2316:
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begin
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if (ir9 != `PHK) begin
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set_sp();
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_PC158;
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state <= STORE1;
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end
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end
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`STW_PC158:
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begin
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set_sp();
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_PC70;
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state <= STORE1;
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end
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`STW_PC70:
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begin
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case({1'b0,ir[7:0]})
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`BRK,`COP:
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begin
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set_sp();
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vpa <= `FALSE;
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vda <= `FALSE;
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store_what <= `STW_SR70;
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state <= STORE1;
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end
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`JSR: begin
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pc[15:0] <= ir[23:8];
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ado <= {pc[23:16],ir[23:8]};
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end
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`JSL: begin
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pc[23:0] <= ir[31:8];
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ado <= ir[31:8];
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end
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`JSR_INDX:
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begin
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vpa <= `FALSE;
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vda <= `FALSE;
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state <= LOAD_MAC1;
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load_what <= `PC_70;
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radr <= absx_address;
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end
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endcase
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end
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`STW_SR70:
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begin
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if (ir[7:0]==`BRK) begin
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load_what <= `PC_70;
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state <= LOAD_MAC1;
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vpa <= `FALSE;
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vda <= `FALSE;
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pc[23:16] <= 8'h00;//abs8[23:16];
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radr <= vect;
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im <= hwi;
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df <= 1'b0;
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end
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else if (ir[7:0]==`COP) begin
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load_what <= `PC_70;
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vpa <= `FALSE;
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vda <= `FALSE;
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state <= LOAD_MAC1;
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pc[23:16] <= 8'h00;//abs8[23:16];
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radr <= vect;
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im <= 1'b1;
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end
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end
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default:
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if (isJsrIndx) begin
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load_what <= `PC_310;
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vpa <= `FALSE;
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vda <= `FALSE;
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state <= LOAD_MAC1;
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radr <= ir[31:8] + x;
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end
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else if (isJsrInd) begin
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load_what <= `PC_310;
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vpa <= `FALSE;
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vda <= `FALSE;
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state <= LOAD_MAC1;
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radr <= ir[31:8];
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end
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endcase
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`ifdef SUPPORT_DCACHE
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if (!dhit && write_allocate) begin
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state <= DCACHE1;
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end
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`endif
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end
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`ifdef SUPPORT_BERR
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else if (err_i) begin
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mlb <= 1'b0;
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data_nack();
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derr_address <= ado[23:0];
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intno <= 9'd508;
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state <= BUS_ERROR;
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end
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`endif
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