repo2/ultimate_cart/veronica/output_mux.vhd @ 1475
| 438 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY output_mux IS
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PORT (
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config_select : in std_logic;
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sram_select : in std_logic;
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config_data : in std_logic_vector(7 downto 0);
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sram_data : in std_logic_vector(7 downto 0);
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read_data : out std_logic_vector(7 downto 0)
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);
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END output_mux;
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ARCHITECTURE vhdl OF output_mux IS
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begin
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process(config_select,sram_select,config_data,sram_data)
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begin
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read_data <= sram_data;
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if (config_select='1') then
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read_data <= config_data;
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end if;
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end process;
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end vhdl;
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