repo2/ultimate_cart/veronica/FT832misc_task.v @ 1475
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// __
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// \\__/ o\ (C) 2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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function [31:0] fn_get_sp;
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input [31:0] sp;
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begin
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if (m832)
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fn_get_sp = {4'd0,sp};
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else if (m816)
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fn_get_sp = {stack_bank,sp[15:0]};
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else
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fn_get_sp = {stack_page,sp[7:0]};
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end
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endfunction
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function [31:0] fn_add_to_sp;
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input [31:0] amt;
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begin
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if (m832)
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fn_add_to_sp = sp + amt;
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else if (m816)
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fn_add_to_sp = {stack_bank,sp[15:0] + amt[15:0]};
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else
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fn_add_to_sp = {stack_page,sp[7:0] + amt[7:0]};
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end
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endfunction
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function [31:0] fn_limit;
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input [3:0] size;
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begin
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case(size)
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4'd0: fn_limit = 32'd0;
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4'd1: fn_limit = 32'd255;
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4'd2: fn_limit = 32'd1023;
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4'd3: fn_limit = 32'd4095;
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4'd4: fn_limit = 32'd16383;
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4'd5: fn_limit = 32'd65535;
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4'd6: fn_limit = 32'd262143;
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4'd7: fn_limit = 32'd1048575;
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4'd8: fn_limit = 32'd4194303;
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4'd9: fn_limit = 32'd16777215;
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4'd10: fn_limit = 32'd67108863;
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4'd11: fn_limit = 32'd268435454;
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4'd12: fn_limit = 32'd1073741823;
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4'd13: fn_limit = 32'd4294967295; // one less
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default: fn_limit = 32'd4095;
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endcase
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end
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endfunction
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task set_sp;
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begin
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radr <= fn_get_sp(sp);
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wadr <= fn_get_sp(sp);
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sp <= fn_add_to_sp(32'hFFFFFFFF);
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if (m816)
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bank_wrap <= TRUE;
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else if (!m832)
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page_wrap <= TRUE;
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end
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endtask
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task inc_sp;
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begin
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radr <= fn_add_to_sp(32'd1);
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sp <= fn_add_to_sp(32'd1);
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if (m816)
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bank_wrap <= TRUE;
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else if (!m832)
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page_wrap <= TRUE;
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end
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endtask
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function [31:0] fn_sp_inc;
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input [31:0] sp_inc;
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begin
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fn_sp_inc = fn_add_to_sp(32'd1);
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end
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endfunction
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task tsk_push;
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input [5:0] SW8;
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input szFlg;
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input szFlg2;
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begin
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if (m832) begin
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if (szFlg2) begin
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radr <= fn_add_to_sp(32'hFFFFFFFD);
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wadr <= fn_add_to_sp(32'hFFFFFFFD);
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sp <= fn_add_to_sp(32'hFFFFFFFC);
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store_what <= SW8;
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s32 <= TRUE;
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end
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else if (szFlg) begin
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radr <= fn_add_to_sp(32'hFFFFFFFF);
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wadr <= fn_add_to_sp(32'hFFFFFFFF);
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sp <= fn_add_to_sp(32'hFFFFFFFE);
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s16 <= TRUE;
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store_what <= SW8;
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end
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else begin
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radr <= sp;
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wadr <= sp;
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store_what <= SW8;
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sp <= fn_add_to_sp(32'hFFFFFFFF);
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end
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end
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else if (m816) begin
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if (szFlg2) begin
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radr <= fn_add_to_sp(32'hFFFFFFFD);
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wadr <= fn_add_to_sp(32'hFFFFFFFD);
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sp <= fn_add_to_sp(32'hFFFFFFFC);
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store_what <= SW8;
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s32 <= TRUE;
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end
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else if (szFlg) begin
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radr <= fn_add_to_sp(32'hFFFFFFFF);
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wadr <= fn_add_to_sp(32'hFFFFFFFF);
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sp <= fn_add_to_sp(32'hFFFFFFFE);
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s16 <= TRUE;
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store_what <= SW8;
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end
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else begin
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radr <= {stack_bank,sp[15:0]};
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wadr <= {stack_bank,sp[15:0]};
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store_what <= SW8;
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sp <= fn_add_to_sp(32'hFFFFFFFF);;
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end
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bank_wrap <= TRUE;
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end
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else begin
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// We could be pushing the CS or DS from
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// emulation mode.
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if (szFlg2) begin
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radr <= fn_add_to_sp(32'hFFFFFFFD);
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wadr <= fn_add_to_sp(32'hFFFFFFFD);
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sp <= fn_add_to_sp(32'hFFFFFFFC);
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store_what <= SW8;
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s32 <= TRUE;
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end
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else if (szFlg) begin
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radr <= fn_add_to_sp(32'hFFFFFFFF);
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wadr <= fn_add_to_sp(32'hFFFFFFFF);
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sp <= fn_add_to_sp(32'hFFFFFFFE);
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s16 <= TRUE;
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store_what <= SW8;
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end
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else begin
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radr <= {stack_page,sp[7:0]};
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wadr <= {stack_page,sp[7:0]};
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store_what <= SW8;
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sp <= fn_add_to_sp(32'hFFFFFFFF);
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end
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page_wrap <= TRUE;
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end
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data_nack();
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seg <= ss_base;
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lmt <= ss_limit;
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state <= STORE1;
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end
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endtask
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task moveto_ifetch;
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begin
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next_state(ssm ? SSM1 : IFETCH);
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end
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endtask
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