repo2/ultimate_cart/veronica/FT816Sys.v @ 1475
| 438 | markw | `timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT816Sys.v
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// - Top Module for 16 bit CPU
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`define TRUE 1'b1
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`define FALSE 1'b0
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module FT816Sys(btn, xclk, Led, sw);
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input [5:0] btn;
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input xclk;
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output [7:0] Led;
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reg [7:0] Led;
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input [7:0] sw;
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wire xreset = ~btn[0];
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wire irq = btn[1];
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reg [32:0] rommem [2047:0];
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reg [7:0] rammem [8191:0];
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wire rw;
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wire [23:0] ad;
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tri [7:0] db;
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wire cs0,cs1,cs4,cs6;
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initial begin
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`include "..\..\software\asm\test816.ver"
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end
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wire locked;
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wire clk200u,clk85u,clk;
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BUFG bg5 (.I(clk85u), .O(clk) );
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DCM dcm0(
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.RST(xreset),
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.PSCLK(gnd),
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.PSEN(gnd),
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.PSINCDEC(gnd),
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.DSSEN(gnd),
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.CLKIN(xclk),
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.CLKFB(clk200u), // 200.000 MHz
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.CLKDV(),
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.CLKFX(clk85u), // 85.714 MHz unbuffered
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.CLKFX180(),
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.CLK0(),
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.CLK2X(clk200u), // 200.xxx MHz
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.CLK2X180(),
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.CLK90(),
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.CLK180(),
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.CLK270(),
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.LOCKED(locked),
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.PSDONE(),
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.STATUS()
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);
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defparam dcm0.CLK_FEEDBACK = "2x";
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defparam dcm0.CLKDV_DIVIDE = 5.0;
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defparam dcm0.CLKFX_DIVIDE = 25; // (16/25)*100 = 64 MHz
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defparam dcm0.CLKFX_MULTIPLY = 16;
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defparam dcm0.CLKIN_DIVIDE_BY_2 = "FALSE";
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defparam dcm0.CLKIN_PERIOD = 10.000;
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defparam dcm0.CLKOUT_PHASE_SHIFT = "NONE";
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defparam dcm0.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
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defparam dcm0.DFS_FREQUENCY_MODE = "LOW";
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defparam dcm0.DLL_FREQUENCY_MODE = "LOW";
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defparam dcm0.DUTY_CYCLE_CORRECTION = "FALSE";
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// defparam dcm0.FACTORY_JF = 16'h8080;
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defparam dcm0.PHASE_SHIFT = 0;
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defparam dcm0.STARTUP_WAIT = "FALSE";
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always @(posedge clk)
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if (~locked)
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Led <= 8'h00;
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else begin
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if (~cs0 && ~rw && ad[7:0]==8'h00)
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Led <= db;
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end
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always @(posedge clk)
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if (~cs6 & ~rw)
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rammem[ad[12:0]] <= db;
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reg [7:0] ro;
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always @*
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case(ad[1:0])
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2'd0: ro <= rommem[ad[12:2]][7:0];
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2'd1: ro <= rommem[ad[12:2]][15:8];
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2'd2: ro <= rommem[ad[12:2]][23:16];
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2'd3: ro <= rommem[ad[12:2]][31:24];
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endcase
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assign db = rw & ~cs1 ? sw : {8{1'bz}};
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assign db = rw & ~cs4 ? ro : {8{1'bz}};
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assign db = rw & ~cs6 ? rammem[ad[12:0]] : {8{1'bz}};
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FT816mpu u1
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(
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.rst(~locked),
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.clk(clk),
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.phi11(),
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.phi12(),
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.phi81(),
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.phi82(),
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.rdy(1'b1),
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.e(),
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.mx(),
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.nmi(1'b0),
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.irq(btn[1]),
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.be(1'b1),
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.vpa(),
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.vda(),
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.mlb(),
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.vpb(),
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.rw(rw),
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.ad(ad),
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.db(db),
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.cs0(cs0),
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.cs1(cs1),
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.cs2(),
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.cs3(),
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.cs4(cs4),
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.cs5(),
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.cs6(cs6)
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);
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endmodule
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