repo2/ultimate_cart/veronica/FT816Float_tb.v @ 1475
| 438 | markw | `timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT816Float_tb.v
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// - Test Bench for triple precision floating point accelerator
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module FT816Float_tb();
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reg clk;
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reg rst;
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reg vda;
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reg rw;
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reg [23:0] ad;
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wire [7:0] db;
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reg [7:0] dbo;
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wire rdy;
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reg [7:0] state;
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reg [7:0] retstate;
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reg fix2flt;
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reg [95:0] value;
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initial begin
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#1 clk <= 1'b0;
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#5 rst <= 1'b1;
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#100 rst <= 1'b0;
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end
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always #5 clk <= ~clk;
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assign db = rw ? {8{1'bz}} : dbo;
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FT816Float u1 (
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.rst(rst),
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.clk(clk),
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.vda(vda),
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.rw(rw),
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.ad(ad),
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.db(db),
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.rdy(rdy)
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);
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always @(posedge clk)
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if (rst)
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state <= 8'h00;
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else begin
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state <= state + 8'd1;
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case(state)
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8'h00: begin
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value <= 96'h00000000000000004D20000; // MAXINT
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fix2flt <= 1'b1;
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state <= 8'h80;
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retstate <= 8'h01;
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b_write(24'hFEA20F,8'd17); // prime bus
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end
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8'h01: if (rdy) b_write(24'hFEA20F,8'd17); else state <= state;// SWAP
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8'h03: if (rdy) b_read(24'hFEA20F); else state <= state;
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8'h04: if (rdy) begin
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if (db[7]) state <= state - 1;
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end
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else
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state <= state;
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8'h05: begin
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value <= 96'h000000000000000004D20000; // MAXINT
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fix2flt <= 1'b1;
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state <= 8'h80;
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retstate <= 8'h06;
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end
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8'h06: if (rdy) b_write(24'hFEA20F,8'h06); else state <= state;// MUL
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8'h08: if (rdy) b_read(24'hFEA20F); else state <= state;
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8'h09: if (rdy) begin
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if (db[7]) state <= state - 1;
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end
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else
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state <= state;
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8'h20: state <= state;
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// This subroutine writes a value to FAC1.
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8'h80: if (rdy) b_write(24'hFEA200,value[7:0]); else state <= state;
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8'h81: if (rdy) b_write(24'hFEA201,value[15:8]); else state <= state;
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8'h82: if (rdy) b_write(24'hFEA202,value[23:16]); else state <= state;
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8'h83: if (rdy) b_write(24'hFEA203,value[31:24]); else state <= state;
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8'h84: if (rdy) b_write(24'hFEA204,value[39:32]); else state <= state;
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8'h85: if (rdy) b_write(24'hFEA205,value[47:40]); else state <= state;
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8'h86: if (rdy) b_write(24'hFEA206,value[55:48]); else state <= state;
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8'h87: if (rdy) b_write(24'hFEA207,value[63:56]); else state <= state;
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8'h88: if (rdy) b_write(24'hFEA208,value[71:64]); else state <= state;
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8'h89: if (rdy) b_write(24'hFEA209,value[79:72]); else state <= state;
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8'h8A: if (rdy) b_write(24'hFEA20A,value[87:80]); else state <= state;
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8'h8B: if (rdy) begin b_write(24'hFEA20B,value[95:88]); if (fix2flt) state <= 8'h90; else state <= retstate; end else state <= state;
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8'h90: if (rdy) b_write(24'hFEA20F,8'h05); else state <= state;// FIX2FLT
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8'h92: if (rdy) b_read(24'hFEA20F); else state <= state;
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8'h93: if (rdy) begin
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if (db[7]) state <= state - 1;
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else state <= retstate;
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end
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else
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state <= state;
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endcase
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end
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task b_write;
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input [23:0] adr;
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input [7:0] dat;
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begin
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vda <= 1'b1;
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rw <= 1'b0;
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ad <= adr;
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dbo <= dat;
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end
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endtask
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task b_read;
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input [23:0] adr;
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begin
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vda <= 1'b1;
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rw <= 1'b1;
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ad <= adr;
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end
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endtask
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endmodule
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