repo2/mist/DualPortRAM.vhd @ 1475
| 1316 | markw | -- Generic dual-port RAM implementation -
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-- will hopefully work for both Altera and Xilinx parts
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library ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY DualPortRAM IS
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GENERIC
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(
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addrbits : integer := 9;
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databits : integer := 7
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);
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PORT
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(
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address_a : IN STD_LOGIC_VECTOR (addrbits-1 downto 0);
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address_b : IN STD_LOGIC_VECTOR (addrbits-1 downto 0);
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clock : IN STD_LOGIC := '1';
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data_a : IN STD_LOGIC_VECTOR (databits-1 downto 0);
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data_b : IN STD_LOGIC_VECTOR (databits-1 downto 0);
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wren_a : IN STD_LOGIC := '0';
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wren_b : IN STD_LOGIC := '0';
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q_a : OUT STD_LOGIC_VECTOR (databits-1 downto 0);
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q_b : OUT STD_LOGIC_VECTOR (databits-1 downto 0)
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);
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END DualPortRAM;
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architecture arch of DualPortRAM is
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type ram_type is array(natural range ((2**addrbits)-1) downto 0) of std_logic_vector(databits-1 downto 0);
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shared variable ram : ram_type;
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begin
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-- Port A
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process (clock)
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begin
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if (clock'event and clock = '1') then
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if wren_a='1' then
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ram(to_integer(unsigned(address_a))) := data_a;
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q_a <= data_a;
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else
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q_a <= ram(to_integer(unsigned(address_a)));
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end if;
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end if;
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end process;
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-- Port B
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process (clock)
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begin
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if (clock'event and clock = '1') then
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if wren_b='1' then
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ram(to_integer(unsigned(address_b))) := data_b;
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q_b <= data_b;
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else
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q_b <= ram(to_integer(unsigned(address_b)));
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end if;
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end if;
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end process;
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end architecture;
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