repo2/eclaireXL_ITX/pll_gclk.spd @ 1475
| 479 | markw | <?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file path="pll_gclk_sim/pll_gclk.vho" type="VHDL" />
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<topLevel name="pll_gclk" />
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<deviceFamily name="cyclonev" />
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</simPackage>
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