repo2/eclaireXL_ITX/hdmi/infopacketstate.v @ 1475
| 951 | markw | module infopacketstate (
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clock , // clock
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reset , // Active high, syn reset
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start_of_frame,
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audio_regen_needed,
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packet_sent,
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audio_regen,
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audio_info,
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video_info,
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packet_needed
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);
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//-------------Input Ports-----------------------------
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input clock,reset,start_of_frame,audio_regen_needed,packet_sent;
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//-------------Output Ports----------------------------
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output audio_regen,audio_info,video_info,packet_needed;
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//-------------Input ports Data Type-------------------
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wire clock,reset,start_of_frame,audio_regen_needed,packet_sent;
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//-------------Output Ports Data Type------------------
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reg audio_regen,audio_info,video_info,packet_needed;
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//-------------Internal Constants--------------------------
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parameter SIZE = 5 ;
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parameter CHOOSE = 2'b00,AUDIO_REGEN = 2'b01,AUDIO_INFO = 2'b10,VIDEO_INFO = 2'b11;
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//-------------Internal Variables---------------------------
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reg [SIZE-1:0] state ;// Seq part of the FSM
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wire [SIZE-1:0] next_state ;// combo part of FSM
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//----------Code startes Here------------------------
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assign next_state = fsm_function(state,start_of_frame,audio_regen_needed,packet_sent);
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//----------Function for Combo Logic-----------------
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function [SIZE-1:0] fsm_function;
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input [SIZE-1:0] state ;
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input start_of_frame ;
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input audio_regen_needed ;
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input packet_sent ;
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fsm_function[4] = start_of_frame | state[4]; //video_info
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fsm_function[3] = start_of_frame | state[3]; //audio_info
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fsm_function[2] = audio_regen_needed | state[2]; //audio_regen
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fsm_function[1:0] = state[1:0];
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case(state[1:0])
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CHOOSE : if (state[2] == 1'b1) begin
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fsm_function[1:0] = AUDIO_REGEN;;
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end else if (state[3] == 1'b1) begin
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fsm_function[1:0] = AUDIO_INFO;
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end else if (state[4] == 1'b1) begin
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fsm_function[1:0] = VIDEO_INFO;
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end
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AUDIO_REGEN : if (packet_sent == 1'b1) begin
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fsm_function[1:0] = CHOOSE;
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fsm_function[2] = 0;
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end
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AUDIO_INFO : if (packet_sent == 1'b1) begin
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fsm_function[1:0] = CHOOSE;
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fsm_function[3] = 0;
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end
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VIDEO_INFO : if (packet_sent == 1'b1) begin
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fsm_function[1:0] = CHOOSE;
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fsm_function[4] = 0;
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end
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default : fsm_function = CHOOSE;
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endcase
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endfunction
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//----------Seq Logic-----------------------------
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always @ (posedge clock)
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begin : FSM_SEQ
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if (reset == 1'b1) begin
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state <= #1 CHOOSE;
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end else begin
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state <= #1 next_state;
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end
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end
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//----------Output Logic-----------------------------
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always @ (posedge clock)
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begin : OUTPUT_LOGIC
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if (reset == 1'b1) begin
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audio_regen <= #1 1'b0;
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video_info <= #1 1'b0;
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audio_info <= #1 1'b0;
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packet_needed <= #1 1'b0;
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end
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else begin
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case(state[1:0])
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CHOOSE : begin
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audio_regen <= #1 1'b0;
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video_info <= #1 1'b0;
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audio_info <= #1 1'b0;
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packet_needed <= #1 1'b0;
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end
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AUDIO_REGEN : begin
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audio_regen <= #1 1'b1;
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video_info <= #1 1'b0;
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audio_info <= #1 1'b0;
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packet_needed <= #1 1'b1;
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end
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AUDIO_INFO : begin
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audio_regen <= #1 1'b0;
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video_info <= #1 1'b0;
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audio_info <= #1 1'b1;
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packet_needed <= #1 1'b1;
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end
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VIDEO_INFO : begin
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audio_regen <= #1 1'b0;
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video_info <= #1 1'b1;
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audio_info <= #1 1'b0;
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packet_needed <= #1 1'b1;
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end
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default : begin
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audio_regen <= #1 1'b0;
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video_info <= #1 1'b0;
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audio_info <= #1 1'b0;
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packet_needed <= #1 1'b0;
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end
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endcase
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end
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end // End Of Block OUTPUT_LOGIC
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endmodule // End of Module arbiter
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