repo2/eclaireXL_ITX/hdmi/hdmidelay.vhd @ 1475
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-- (c) 2016 Alexey Spirkov
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-- I am happy for anyone to use this for non-commercial use.
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-- If my verilog/vhdl/c files are used commercially or otherwise sold,
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-- please contact me for explicit permission at me _at_ alsp.net.
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-- This applies for source and binary form and derived works.
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library ieee;
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use ieee.std_logic_1164.all;
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entity hdmi_delay_line is
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generic(
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G_WIDTH : integer := 40;
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G_DEPTH : integer := 11);
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port (
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I_CLK : in std_logic;
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I_D : in std_logic_vector(G_WIDTH-1 downto 0);
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O_Q : out std_logic_vector(G_WIDTH-1 downto 0));
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end hdmi_delay_line;
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architecture rtl of hdmi_delay_line is
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type t_q_pipe is array(0 to G_DEPTH-1) of std_logic_vector(G_WIDTH-1 downto 0);
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signal q_pipe : t_q_pipe;
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begin
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process_pipe : process(i_clk)
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begin
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if(rising_edge(i_clk)) then
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q_pipe <= I_D&q_pipe(0 to q_pipe'length-2);
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end if;
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end process process_pipe;
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O_Q <= q_pipe(q_pipe'length-1);
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end rtl;
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