repo2/eclaireXL_ITX/hdmi/dvi.vhd @ 1475
| 479 | markw | -------------------------------------------------------------------[09.05.2016]
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| 483 | markw | -- DVI
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| 479 | markw | -------------------------------------------------------------------------------
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-- Engineer: MVV
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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| 483 | markw | entity dvi is
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| 479 | markw | port (
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I_CLK_PIXEL : in std_logic; -- pixelclock
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I_HSYNC : in std_logic;
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I_VSYNC : in std_logic;
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I_BLANK : in std_logic;
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I_RED : in std_logic_vector(7 downto 0);
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I_GREEN : in std_logic_vector(7 downto 0);
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I_BLUE : in std_logic_vector(7 downto 0);
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| 483 | markw | O_R : out std_logic_vector(9 downto 0);
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O_G : out std_logic_vector(9 downto 0);
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O_B : out std_logic_vector(9 downto 0));
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end entity dvi;
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architecture rtl of dvi is
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| 479 | markw | signal r : std_logic_vector(9 downto 0);
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signal g : std_logic_vector(9 downto 0);
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signal b : std_logic_vector(9 downto 0);
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| 483 | markw | ||
| 479 | markw | begin
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encode_r : entity work.encoder
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port map (
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| 483 | markw | CLK => I_CLK_PIXEL,
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DATA => I_RED,
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C => "00",
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VDE => not(I_BLANK),
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ENCODED => r);
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| 479 | markw | ||
encode_g : entity work.encoder
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port map (
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| 483 | markw | CLK => I_CLK_PIXEL,
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DATA => I_GREEN,
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C => "00",
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VDE => not(I_BLANK),
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ENCODED => g);
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| 479 | markw | ||
encode_b : entity work.encoder
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port map (
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| 483 | markw | CLK => I_CLK_PIXEL,
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DATA => I_BLUE,
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C => (I_VSYNC & I_HSYNC),
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VDE => not(I_BLANK),
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ENCODED => b);
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| 479 | markw | ||
| 483 | markw | o_r <= r;
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o_g <= g;
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o_b <= b;
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| 479 | markw | ||
end architecture rtl;
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