repo2/eclaireXL_ITX/clkctrl/synthesis/clkctrl.vhd @ 1475
| 479 | markw | -- clkctrl.vhd
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-- Generated using ACDS version 16.1 196
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity clkctrl is
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port (
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inclk : in std_logic := '0'; -- altclkctrl_input.inclk
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ena : in std_logic := '0'; -- .ena
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outclk : out std_logic -- altclkctrl_output.outclk
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);
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end entity clkctrl;
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architecture rtl of clkctrl is
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component clkctrl_altclkctrl_0 is
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port (
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inclk : in std_logic := 'X'; -- inclk
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ena : in std_logic := 'X'; -- ena
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outclk : out std_logic -- outclk
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);
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end component clkctrl_altclkctrl_0;
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begin
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altclkctrl_0 : component clkctrl_altclkctrl_0
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port map (
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inclk => inclk, -- altclkctrl_input.inclk
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ena => ena, -- .ena
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outclk => outclk -- altclkctrl_output.outclk
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);
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end architecture rtl; -- of clkctrl
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