repo2/eclaireXL_ITX/clkctrl/clkctrl_inst.vhd @ 1475
| 479 | markw | component clkctrl is
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port (
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inclk : in std_logic := 'X'; -- inclk
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ena : in std_logic := 'X'; -- ena
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outclk : out std_logic -- outclk
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);
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end component clkctrl;
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u0 : component clkctrl
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port map (
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inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
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ena => CONNECTED_TO_ena, -- .ena
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outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
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);
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