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Revision 147

Added by markw about 11 years ago

Changes for Aeon lite - notably 1MB ram support and ise build warnings fixed

View differences:

common/a8core/atari800core.vhd
(
cycle_length : integer := 16; -- or 32...
video_bits : integer := 8;
palette : integer :=1 -- 0:gtia colour on VIDEO_B, 1:altirra, 2:laoo
palette : integer :=1; -- 0:gtia colour on VIDEO_B, 1:altirra, 2:laoo
low_memory : integer := 0 -- 0:8MB memory map, 1:1MB memory map
);
PORT
(
......
PORTB_OUT => PORTB_OUT_INT);
mmu1 : entity work.address_decoder
GENERIC MAP(low_memory => low_memory)
PORT MAP(CLK => CLK,
CPU_FETCH => CPU_FETCH,
CPU_WRITE_N => R_W_N,
common/a8core/atari800core_simple_sdram.vhd
-- For initial port may help to have no
internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
internal_ram : integer := 16384 -- at start of memory map
internal_ram : integer := 16384; -- at start of memory map
-- Use 1MB memory map if low memory set (for Aeon lite)
low_memory : integer := 0
);
PORT
(
......
(
cycle_length => cycle_length,
video_bits => video_bits,
palette => palette
palette => palette,
low_memory => low_memory
)
PORT MAP
(
common/a8core/ps2_to_atari800.vhdl
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- (ILoveSpeccy) Added PS2_KEYS Output
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
CONSOL_SELECT : OUT STD_LOGIC;
CONSOL_OPTION : OUT STD_LOGIC;
FKEYS : OUT STD_LOGIC_VECTOR(11 downto 0)
FKEYS : OUT STD_LOGIC_VECTOR(11 downto 0);
PS2_KEYS : OUT STD_LOGIC_VECTOR(511 downto 0)
);
END ps2_to_atari800;
......
SIGNAL SHIFT_PRESSED : STD_LOGIC;
SIGNAL BREAK_PRESSED : STD_LOGIC;
SIGNAL CONTROL_PRESSED : STD_LOGIC;
BEGIN
BEGIN
PS2_KEYS <= ps2_keys_reg;
keyboard1: entity work.ps2_keyboard
PORT MAP
(
common/components/scandoubler.vhdl
signal b_reg : std_logic_vector(7 downto 0);
signal linea_address : std_logic_vector(10 downto 0);
signal linea_address_integer : integer;
signal linea_write_enable : std_logic;
signal linea_out : std_logic_vector(7 downto 0);
signal lineb_address : std_logic_vector(10 downto 0);
signal lineb_address_integer : integer;
signal lineb_write_enable : std_logic;
signal lineb_out : std_logic_vector(7 downto 0);
......
--lineb : reg_file
-- generic map (BYTES=>456,WIDTH=>9)
-- port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);
linea_address_integer <= to_integer(unsigned(linea_address));
linea : scandouble_ram_infer
port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
port map (clock=>clk,address=>linea_address_integer,we=>linea_write_enable,data=>colour_in,q=>linea_out);
lineb_address_integer <= to_integer(unsigned(lineb_address));
lineb : scandouble_ram_infer
port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);
port map (clock=>clk,address=>lineb_address_integer,we=>lineb_write_enable,data=>colour_in,q=>lineb_out);
-- capture
process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
common/zpu/zpu_config_regs.vhdl
signal spi_dma_addr_reg : std_logic_vector(15 downto 0);
signal spi_dma_addrend_reg : std_logic_vector(15 downto 0);
signal spi_dma_reg : std_logic;
signal spi_clk_div_integer : integer;
signal spi_addr_integer : integer;
begin
-- register
process(clk,reset_n)
......
-- spi - for sd card access without bit banging...
-- 200KHz to start with - probably fine for 8-bit, can up it later after init
spi_clk_div_integer <= to_integer(unsigned(spi_speed_reg));
spi_addr_integer <= to_integer(unsigned(vectorize(spi_addr_reg)));
spi_master1 : entity work.spi_master
generic map(slaves=>1,d_width=>8)
port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
port map (clock=>clk,reset_n=>reset_n,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>spi_clk_div_integer,addr=>spi_addr_integer,
tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
rx_data=>spi_rx_data,busy=>spi_busy);
......
if (spi_busy = '0') then
spi_dma_wr <= '1';
spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+1);
spi_dma_addr_next <= std_logic_vector(unsigned(spi_dma_addr_reg)+to_unsigned(1,16));
spi_dma_next <= '0';
if (not(spi_dma_addr_next = spi_dma_addrend_reg)) then

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