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/* Startup code for ZPU
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Copyright (C) 2005 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 2, or (at your option) any
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later version.
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In addition to the permissions in the GNU General Public License, the
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Free Software Foundation gives you unlimited permission to link the
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compiled version of this file with other programs, and to distribute
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those programs without any restriction coming from the use of this
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file. (The General Public License restrictions do apply in other
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respects; for example, they cover modification of the file, and
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distribution when not linked into another program.)
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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.file "mincrt0.S"
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/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
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.section ".fixed_vectors","ax"
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; KLUDGE!!! we remove the executable bit to avoid relaxation
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.section ".fixed_vectors","a"
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.macro fixedim value
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im \value
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.endm
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.macro jmp address
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fixedim \address
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poppc
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.endm
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.macro fast_neg
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not
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im 1
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add
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.endm
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.macro mult1bit
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; create mask of lowest bit in A
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loadsp 8 ; A
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im 1
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and
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im -1
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add
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not
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loadsp 8 ; B
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and
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add ; accumulate in C
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; shift B left 1 bit
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loadsp 4 ; B
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addsp 0
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storesp 8 ; B
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; shift A right 1 bit
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loadsp 8 ; A
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flip
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addsp 0
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flip
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storesp 12 ; A
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.endm
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.macro cimpl funcname
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; save R0
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im _memreg
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load
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; save R1
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im _memreg+4
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load
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; save R2
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im _memreg+8
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load
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loadsp 20
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loadsp 20
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fixedim \funcname
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call
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; destroy arguments on stack
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storesp 0
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storesp 0
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im _memreg
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load
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; poke the result into the right slot
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storesp 24
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; restore R2
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im _memreg+8
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store
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; restore R1
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im _memreg+4
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store
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; restore r0
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im _memreg
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store
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storesp 4
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poppc
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.endm
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.globl _start
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_start:
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jmp _premain
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/* vectors */
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/* instruction emulation code */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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# opcode 34
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# offset 0x0000 0040
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.balign 32,0
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_loadh:
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loadsp 4
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; by not masking out bit 0, we cause a memory access error
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; on unaligned access
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im ~0x2
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and
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load
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; mult 8
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loadsp 8
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im 3
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and
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fast_neg
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im 2
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add
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im 3
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ashiftleft
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; shift right addr&3 * 8
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lshiftright
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im 0xffff
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and
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storesp 8
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poppc
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# opcode 35
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# offset 0x0000 0060
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.balign 32,0
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_storeh:
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loadsp 4
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; by not masking out bit 0, we cause a memory access error
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; on unaligned access
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im ~0x2
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and
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load
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; mask
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im 0xffff
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loadsp 12
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im 3
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and
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fast_neg
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im 2
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add
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im 3
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ashiftleft
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ashiftleft
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not
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and
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loadsp 12
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im 0xffff
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nop
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fixedim _storehtail
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poppc
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# opcode 36
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# offset 0x0000 0080
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.balign 32,0
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_lessthan:
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loadsp 8
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fast_neg
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loadsp 8
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add
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; DANGER!!!!
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; 0x80000000 will overflow when negated, so we need to mask
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; the result above with the compare positive to negative
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; number case
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loadsp 12
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loadsp 12
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not
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and
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not
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and
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; handle case where we are comparing a negative number
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; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
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loadsp 12
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not
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loadsp 12
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and
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or
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flip
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im 1
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and
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storesp 12
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storesp 4
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poppc
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# opcode 37
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# offset 0x0000 00a0
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.balign 32,0
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_lessthanorequal:
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loadsp 8
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loadsp 8
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lessthan
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loadsp 12
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loadsp 12
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eq
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or
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storesp 12
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storesp 4
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poppc
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# opcode 38
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# offset 0x0000 00c0
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.balign 32,0
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_ulessthan:
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; fish up arguments
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loadsp 4
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loadsp 12
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/* low: -1 if low bit dif is negative 0 otherwise: neg (not x&1 and (y&1))
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x&1 y&1 neg (not x&1 and (y&1))
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1 1 0
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1 0 0
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0 1 -1
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0 0 0
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*/
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loadsp 4
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not
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loadsp 4
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and
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im 1
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and
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neg
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/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
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high=x>>1 - y>>1 + low
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extremes
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0000 - 1111:
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low= neg(not 0 and 1) = 1111 (-1)
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high=000+ neg(111) +low = 000 + 1001 + low = 1000
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OK
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1111 - 0000
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low=neg(not 1 and 0) = 0
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high=111+neg(000) + low = 0111
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OK
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*/
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loadsp 8
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flip
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addsp 0
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flip
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loadsp 8
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flip
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addsp 0
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flip
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sub
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; if they are equal, then the last bit decides...
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add
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/* test if negative: result = flip(diff) & 1 */
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flip
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im 1
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and
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; destroy a&b which are on stack
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storesp 4
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storesp 4
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storesp 12
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storesp 4
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poppc
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# opcode 39
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# offset 0x0000 00e0
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.balign 32,0
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_ulessthanorequal:
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loadsp 8
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loadsp 8
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ulessthan
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loadsp 12
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loadsp 12
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eq
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or
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storesp 12
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storesp 4
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poppc
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# opcode 40
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# offset 0x0000 0100
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.balign 32,0
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.globl _swap
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_swap:
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breakpoint ; tbd
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# opcode 41
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# offset 0x0000 0120
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.balign 32,0
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_slowmult:
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im _slowmultImpl
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poppc
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# opcode 42
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# offset 0x0000 0140
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.balign 32,0
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_lshiftright:
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loadsp 8
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flip
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loadsp 8
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ashiftleft
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flip
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storesp 12
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storesp 4
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poppc
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# opcode 43
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# offset 0x0000 0160
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.balign 32,0
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_ashiftleft:
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loadsp 8
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loadsp 8
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im 0x1f
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and
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fast_neg
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im _ashiftleftEnd
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add
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poppc
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# opcode 44
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# offset 0x0000 0180
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.balign 32,0
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_ashiftright:
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loadsp 8
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loadsp 8
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lshiftright
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; handle signed value
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im -1
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loadsp 12
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im 0x1f
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and
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lshiftright
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not ; now we have an integer on the stack with the signed
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; bits in the right position
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; mask these bits with the signed bit.
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loadsp 16
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not
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flip
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im 1
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and
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im -1
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add
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and
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; stuff in the signed bits...
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or
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; store result into correct stack slot
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storesp 12
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; move up return value
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storesp 4
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poppc
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# opcode 45
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# offset 0x0000 01a0
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.balign 32,0
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_call:
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; fn
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loadsp 4
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; return address
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loadsp 4
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; store return address
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storesp 12
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; fn to call
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storesp 4
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pushsp ; flush internal stack
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popsp
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poppc
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_storehtail:
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and
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loadsp 12
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im 3
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and
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fast_neg
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im 2
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add
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im 3
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ashiftleft
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nop
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ashiftleft
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or
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loadsp 8
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im ~0x3
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and
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store
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storesp 4
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storesp 4
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poppc
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# opcode 46
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# offset 0x0000 01c0
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.balign 32,0
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_eq:
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loadsp 8
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fast_neg
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loadsp 8
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add
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|
|
not
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loadsp 0
|
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im 1
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add
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not
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and
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flip
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im 1
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and
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|
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storesp 12
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storesp 4
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poppc
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|
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# opcode 47
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# offset 0x0000 01e0
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.balign 32,0
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_neq:
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loadsp 8
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fast_neg
|
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loadsp 8
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add
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|
|
not
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loadsp 0
|
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im 1
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add
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not
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and
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flip
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|
not
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im 1
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and
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storesp 12
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storesp 4
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poppc
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|
|
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# opcode 48
|
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# offset 0x0000 0200
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.balign 32,0
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_neg:
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loadsp 4
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not
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im 1
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add
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storesp 8
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|
poppc
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|
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# opcode 49
|
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# offset 0x0000 0220
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.balign 32,0
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_sub:
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loadsp 8
|
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loadsp 8
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fast_neg
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add
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storesp 12
|
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|
|
storesp 4
|
|
|
|
poppc
|
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|
|
|
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# opcode 50
|
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# offset 0x0000 0240
|
|
.balign 32,0
|
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_xor:
|
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loadsp 8
|
|
not
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|
loadsp 8
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|
and
|
|
|
|
loadsp 12
|
|
loadsp 12
|
|
not
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and
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|
|
|
or
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|
|
storesp 12
|
|
storesp 4
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|
poppc
|
|
|
|
# opcode 51
|
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# offset 0x0000 0260
|
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.balign 32,0
|
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_loadb:
|
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loadsp 4
|
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im ~0x3
|
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and
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load
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|
|
|
loadsp 8
|
|
im 3
|
|
and
|
|
fast_neg
|
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im 3
|
|
add
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; x8
|
|
addsp 0
|
|
addsp 0
|
|
addsp 0
|
|
|
|
lshiftright
|
|
|
|
im 0xff
|
|
and
|
|
storesp 8
|
|
|
|
poppc
|
|
|
|
|
|
# opcode 52
|
|
# offset 0x0000 0280
|
|
.balign 32,0
|
|
_storeb:
|
|
loadsp 4
|
|
im ~0x3
|
|
and
|
|
load
|
|
|
|
; mask away destination
|
|
im _mask
|
|
loadsp 12
|
|
im 3
|
|
and
|
|
addsp 0
|
|
addsp 0
|
|
add
|
|
load
|
|
|
|
and
|
|
|
|
|
|
im _storebtail
|
|
poppc
|
|
|
|
# opcode 53
|
|
# offset 0x0000 02a0
|
|
.balign 32,0
|
|
_div:
|
|
jmp ___div
|
|
|
|
# opcode 54
|
|
# offset 0x0000 02c0
|
|
.balign 32,0
|
|
_mod:
|
|
jmp ___mod
|
|
|
|
# opcode 55
|
|
# offset 0x0000 02e0
|
|
.balign 32,0
|
|
.globl _eqbranch
|
|
_eqbranch:
|
|
loadsp 8
|
|
|
|
; eq
|
|
|
|
not
|
|
loadsp 0
|
|
im 1
|
|
add
|
|
not
|
|
and
|
|
flip
|
|
im 1
|
|
and
|
|
|
|
; mask
|
|
im -1
|
|
add
|
|
loadsp 0
|
|
storesp 16
|
|
|
|
; no branch address
|
|
loadsp 4
|
|
|
|
and
|
|
|
|
; fetch boolean & neg mask
|
|
loadsp 12
|
|
not
|
|
|
|
; calc address & mask for branch
|
|
loadsp 8
|
|
loadsp 16
|
|
add
|
|
; subtract 1 to find PC of branch instruction
|
|
im -1
|
|
add
|
|
|
|
and
|
|
|
|
or
|
|
|
|
storesp 4
|
|
storesp 4
|
|
storesp 4
|
|
poppc
|
|
|
|
|
|
# opcode 56
|
|
# offset 0x0000 0300
|
|
.balign 32,0
|
|
.globl _neqbranch
|
|
_neqbranch:
|
|
loadsp 8
|
|
|
|
; neq
|
|
|
|
not
|
|
loadsp 0
|
|
im 1
|
|
add
|
|
not
|
|
and
|
|
flip
|
|
|
|
not
|
|
|
|
im 1
|
|
and
|
|
|
|
; mask
|
|
im -1
|
|
add
|
|
loadsp 0
|
|
storesp 16
|
|
|
|
; no branch address
|
|
loadsp 4
|
|
|
|
and
|
|
|
|
; fetch boolean & neg mask
|
|
loadsp 12
|
|
not
|
|
|
|
; calc address & mask for branch
|
|
loadsp 8
|
|
loadsp 16
|
|
add
|
|
; find address of branch instruction
|
|
im -1
|
|
add
|
|
|
|
and
|
|
|
|
or
|
|
|
|
storesp 4
|
|
storesp 4
|
|
storesp 4
|
|
poppc
|
|
|
|
# opcode 57
|
|
# offset 0x0000 0320
|
|
.balign 32,0
|
|
.globl _poppcrel
|
|
_poppcrel:
|
|
add
|
|
; address of poppcrel
|
|
im -1
|
|
add
|
|
poppc
|
|
|
|
# opcode 58
|
|
# offset 0x0000 0340
|
|
.balign 32,0
|
|
.globl _config
|
|
_config:
|
|
im 1
|
|
nop
|
|
im _hardware
|
|
store
|
|
storesp 4
|
|
poppc
|
|
|
|
# opcode 59
|
|
# offset 0x0000 0360
|
|
.balign 32,0
|
|
_pushpc:
|
|
loadsp 4
|
|
im 1
|
|
add
|
|
storesp 8
|
|
poppc
|
|
|
|
# opcode 60
|
|
# offset 0x0000 0380
|
|
.balign 32,0
|
|
_syscall_emulate:
|
|
.byte 0
|
|
|
|
# opcode 61
|
|
# offset 0x0000 03a0
|
|
.balign 32,0
|
|
_pushspadd:
|
|
pushsp
|
|
im 4
|
|
add
|
|
loadsp 8
|
|
addsp 0
|
|
addsp 0
|
|
add
|
|
storesp 8
|
|
|
|
poppc
|
|
|
|
# opcode 62
|
|
# offset 0x0000 03c0
|
|
.balign 32,0
|
|
_halfmult:
|
|
breakpoint
|
|
|
|
# opcode 63
|
|
# offset 0x0000 03e0
|
|
.balign 32,0
|
|
_callpcrel:
|
|
loadsp 4
|
|
loadsp 4
|
|
add
|
|
im -1
|
|
add
|
|
loadsp 4
|
|
|
|
storesp 12 ; return address
|
|
storesp 4
|
|
pushsp ; this will flush the internal stack.
|
|
popsp
|
|
poppc
|
|
|
|
.text
|
|
|
|
|
|
|
|
|
|
_ashiftleftBegin:
|
|
.rept 0x1f
|
|
addsp 0
|
|
.endr
|
|
_ashiftleftEnd:
|
|
storesp 12
|
|
storesp 4
|
|
poppc
|
|
|
|
_storebtail:
|
|
loadsp 12
|
|
im 0xff
|
|
and
|
|
loadsp 12
|
|
im 3
|
|
and
|
|
|
|
fast_neg
|
|
im 3
|
|
add
|
|
; x8
|
|
addsp 0
|
|
addsp 0
|
|
addsp 0
|
|
|
|
ashiftleft
|
|
|
|
or
|
|
|
|
loadsp 8
|
|
im ~0x3
|
|
and
|
|
|
|
store
|
|
|
|
storesp 4
|
|
storesp 4
|
|
poppc
|
|
|
|
|
|
|
|
|
|
; NB! this is not an EMULATE instruction. It is a varargs fn.
|
|
.globl _syscall
|
|
_syscall:
|
|
syscall
|
|
poppc
|
|
|
|
_slowmultImpl:
|
|
|
|
loadsp 8 ; A
|
|
loadsp 8 ; B
|
|
im 0 ; C
|
|
|
|
.LmoreMult:
|
|
mult1bit
|
|
|
|
; cutoff
|
|
loadsp 8
|
|
.byte (.LmoreMult-.Lbranch)&0x7f+0x80
|
|
.Lbranch:
|
|
neqbranch
|
|
|
|
storesp 4
|
|
storesp 4
|
|
storesp 12
|
|
storesp 4
|
|
poppc
|
|
|
|
___mod:
|
|
cimpl __modsi3
|
|
___div:
|
|
cimpl __divsi3
|
|
|
|
.section ".rodata"
|
|
.balign 4,0
|
|
_mask:
|
|
.long 0x00ffffff
|
|
.long 0xff00ffff
|
|
.long 0xffff00ff
|
|
.long 0xffffff00
|
|
|
|
.section ".text","ax"
|
|
.global _boot
|
|
.balign 4,0
|
|
_boot:
|
|
im 0
|
|
poppc
|
|
|
|
.global _break;
|
|
_break:
|
|
im _break
|
|
poppc ; infinite loop
|
|
|
|
_premain:
|
|
im _break
|
|
nop
|
|
fixedim main
|
|
poppc
|
|
|
|
|
|
.data
|
|
.balign 4,0
|
|
|
|
.globl _hardware
|
|
_hardware:
|
|
.long 0
|
|
.globl _cpu_config
|
|
_cpu_config:
|
|
.long 0
|
|
|
|
|
|
.section ".bss"
|
|
.balign 4,0
|
|
.globl _memreg
|
|
_memreg:
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
|