Revision 1428
Added by markw 11 months ago
| atari_chips/pokeyv2/int_osc/int_osc.bsf | ||
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Copyright (C) 2024 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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| atari_chips/pokeyv2/int_osc/int_osc.html | ||
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</table>
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<table class="blueBar">
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<tr>
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<td class="l">2021.01.13.20:13:30</td>
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<td class="l">2024.08.31.14:17:07</td>
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<td class="r">Datasheet</td>
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</tr>
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</table>
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| ... | ... | |
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<a name="module_int_osc_0"> </a>
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<div>
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<hr/>
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<h2>int_osc_0</h2>altera_int_osc v20.1
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<h2>int_osc_0</h2>altera_int_osc v23.1
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<br/>
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<br/>
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<br/>
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| atari_chips/pokeyv2/int_osc/int_osc.xml | ||
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<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2021.01.13.20:13:30"
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outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/">
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date="2024.08.31.14:17:07"
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outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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| ... | ... | |
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</perimeter>
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<entity
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path=""
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parameterizationKey="int_osc:1.0:AUTO_DEVICE=10M08SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1610565210,AUTO_UNIQUE_ID=(altera_int_osc:20.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=116,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,INFORMATION=The output frequency for 10M02, 10M04, 10M08, 10M16, and 10M25 devices is 55~116MHz <br>The output frequency for 10M40, and 10M50 devices is 35~77MHz <br>,PART_NAME=10M08SCU169C8G)"
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parameterizationKey="int_osc:1.0:AUTO_DEVICE=10M08SCU169C8G,AUTO_DEVICE_FAMILY=MAX 10,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1725106627,AUTO_UNIQUE_ID=(altera_int_osc:23.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=116,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,INFORMATION=The output frequency for 10M02, 10M04, 10M08, 10M16, and 10M25 devices is 55~116MHz <br>The output frequency for 10M40, and 10M50 devices is 35~77MHz <br>,PART_NAME=10M08SCU169C8G)"
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instancePathKey="int_osc"
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kind="int_osc"
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version="1.0"
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name="int_osc">
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<parameter name="AUTO_GENERATION_ID" value="1610565210" />
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<parameter name="AUTO_GENERATION_ID" value="1725106627" />
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<parameter name="AUTO_DEVICE" value="10M08SCU169C8G" />
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
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<generatedFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/synthesis/int_osc.vhd"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/synthesis/int_osc.vhd"
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type="VHDL" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/synthesis/submodules/altera_int_osc.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/synthesis/submodules/altera_int_osc.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/synthesis/submodules/altera_int_osc.sdc"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/synthesis/submodules/altera_int_osc.sdc"
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type="SDC"
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attributes="" />
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</childGeneratedFiles>
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<sourceFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc.qsys" />
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="/home/markw/intelFPGA_lite/20.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
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path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="int_osc">queue size: 0 starting:int_osc "int_osc"</message>
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| ... | ... | |
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_int_osc:20.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=116,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,INFORMATION=The output frequency for 10M02, 10M04, 10M08, 10M16, and 10M25 devices is 55~116MHz <br>The output frequency for 10M40, and 10M50 devices is 35~77MHz <br>,PART_NAME=10M08SCU169C8G"
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parameterizationKey="altera_int_osc:23.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=116,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=MAX 10,DEVICE_ID=08,INFORMATION=The output frequency for 10M02, 10M04, 10M08, 10M16, and 10M25 devices is 55~116MHz <br>The output frequency for 10M40, and 10M50 devices is 35~77MHz <br>,PART_NAME=10M08SCU169C8G"
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instancePathKey="int_osc:.:int_osc_0"
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kind="altera_int_osc"
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version="20.1"
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version="23.1"
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name="altera_int_osc">
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<parameter name="CLOCK_FREQUENCY_2" value="77" />
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<parameter name="CLOCK_FREQUENCY_1" value="116" />
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| ... | ... | |
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<parameter name="DEVICE_ID" value="08" />
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<generatedFiles>
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/synthesis/submodules/altera_int_osc.v"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/synthesis/submodules/altera_int_osc.v"
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type="VERILOG"
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attributes="" />
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<file
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/synthesis/submodules/altera_int_osc.sdc"
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path="/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/synthesis/submodules/altera_int_osc.sdc"
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type="SDC"
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attributes="" />
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</generatedFiles>
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<childGeneratedFiles/>
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<sourceFiles>
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<file
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path="/home/markw/intelFPGA_lite/20.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
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path="/home/markw/intelFPGA_lite/23.1std/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="int_osc" as="int_osc_0" />
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| atari_chips/pokeyv2/int_osc/int_osc_generation.rpt | ||
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Info: Starting: Create simulation model
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation --family="MAX 10" --part=10M08SCU169C8G
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Progress: Loading build_10M08_fullv2/int_osc.qsys
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation --family="MAX 10" --part=10M08SCU169C8G
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Progress: Loading build_sidmax_10M08_full/int_osc.qsys
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Progress: Reading input file
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Progress: Adding int_osc_0 [altera_int_osc 20.1]
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Progress: Adding int_osc_0 [altera_int_osc 23.1]
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Progress: Parameterizing module int_osc_0
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Progress: Building connections
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Progress: Parameterizing connections
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| ... | ... | |
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Info: qsys-generate succeeded.
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Info: Finished: Create simulation model
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Info: Starting: Create Modelsim Project.
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Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/int_osc.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/ --use-relative-paths=true
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Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/int_osc.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/ --use-relative-paths=true
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Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/ directory:
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Info: mentor/msim_setup.tcl
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Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
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Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/ directory:
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Info: sim-script-gen --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/int_osc.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/ --use-relative-paths=true
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Info: Doing: ip-make-simscript --spd=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/int_osc.spd --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/ --use-relative-paths=true
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Info: Generating the following file(s) for XCELIUM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/ directory:
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Info: xcelium/cds.lib
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Info: xcelium/hdl.var
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Info: xcelium/xcelium_setup.sh
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Info: 1 .cds.lib files in xcelium/cds_libs/ directory
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Info: Generating the following file(s) for VCSMX simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/ directory:
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Info: synopsys/vcsmx/synopsys_sim.setup
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Info: synopsys/vcsmx/vcsmx_setup.sh
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Info: Generating the following file(s) for NCSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/ directory:
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Info: cadence/cds.lib
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Info: cadence/hdl.var
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Info: cadence/ncsim_setup.sh
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Info: 1 .cds.lib files in cadence/cds_libs/ directory
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Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/ directory:
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Info: Generating the following file(s) for RIVIERA simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/ directory:
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Info: aldec/rivierapro_setup.tcl
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Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/simulation/.
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Info: Skipping VCS script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation
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Info: Generating the following file(s) for MODELSIM simulator in /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/ directory:
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Info: mentor/msim_setup.tcl
|
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Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/simulation/.
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Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
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Info: Finished: Create Modelsim Project.
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Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc --family="MAX 10" --part=10M08SCU169C8G
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Progress: Loading build_10M08_fullv2/int_osc.qsys
|
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc --family="MAX 10" --part=10M08SCU169C8G
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Progress: Loading build_sidmax_10M08_full/int_osc.qsys
|
||
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Progress: Reading input file
|
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Progress: Adding int_osc_0 [altera_int_osc 20.1]
|
||
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Progress: Adding int_osc_0 [altera_int_osc 23.1]
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Progress: Parameterizing module int_osc_0
|
||
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Progress: Building connections
|
||
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Progress: Parameterizing connections
|
||
| ... | ... | |
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Info: Finished: Create block symbol file (.bsf)
|
||
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Info:
|
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Info: Starting: Create HDL design files for synthesis
|
||
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Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M08_fullv2/int_osc/synthesis --family="MAX 10" --part=10M08SCU169C8G
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||
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Progress: Loading build_10M08_fullv2/int_osc.qsys
|
||
|
Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_sidmax_10M08_full/int_osc/synthesis --family="MAX 10" --part=10M08SCU169C8G
|
||
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Progress: Loading build_sidmax_10M08_full/int_osc.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding int_osc_0 [altera_int_osc 20.1]
|
||
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Progress: Adding int_osc_0 [altera_int_osc 23.1]
|
||
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Progress: Parameterizing module int_osc_0
|
||
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Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
| atari_chips/pokeyv2/int_osc/synthesis/int_osc.debuginfo | ||
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="int_osc" kind="system" version="20.1" fabric="QSYS">
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<!-- Format version 20.1 720 (Future versions may contain additional information.) -->
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<!-- 2021.01.13.20:13:30 -->
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<EnsembleReport name="int_osc" kind="system" version="23.1" fabric="QSYS">
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<!-- Format version 23.1 993 (Future versions may contain additional information.) -->
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<!-- 2024.08.31.14:17:07 -->
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<!-- A collection of modules and connections -->
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<parameter name="clockCrossingAdapter">
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<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
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| ... | ... | |
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</parameter>
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<parameter name="generationId">
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<type>int</type>
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<value>1610565210</value>
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<value>1725106627</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
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| ... | ... | |
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<module
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name="int_osc_0"
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kind="altera_int_osc"
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version="20.1"
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version="23.1"
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path="int_osc_0">
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<!-- Describes a single module. Module parameters are
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the requested settings for a module instance. -->
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| ... | ... | |
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<visible>true</visible>
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<valid>true</valid>
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</parameter>
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<interface name="oscena" kind="conduit_end" version="20.1">
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<interface name="oscena" kind="conduit_end" version="23.1">
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<!-- The connection points exposed by a module instance for the
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particular module parameters. Connection points and their
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parameters are a RESULT of the module parameters. -->
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||
| ... | ... | |
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<role>oscena</role>
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</port>
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</interface>
|
||
|
<interface name="clkout" kind="clock_source" version="20.1">
|
||
|
<interface name="clkout" kind="clock_source" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||
|
<displayName>Internal Oscillator</displayName>
|
||
|
<version>20.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Conduit</displayName>
|
||
|
<version>20.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Clock Output</displayName>
|
||
|
<version>20.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<reportVersion>20.1 720</reportVersion>
|
||
|
<uniqueIdentifier>F44D30F4F5CE00000176FD2AD272</uniqueIdentifier>
|
||
|
<reportVersion>23.1 993</reportVersion>
|
||
|
<uniqueIdentifier>02424E4C123F00000191A85E239F</uniqueIdentifier>
|
||
|
</EnsembleReport>
|
||
| atari_chips/pokeyv2/int_osc/synthesis/int_osc.qip | ||
|---|---|---|
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_NAME "Qsys"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_VERSION "20.1"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_VERSION "23.1"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_ENV "Qsys"
|
||
|
set_global_assignment -library "int_osc" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../int_osc.sopcinfo"]
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name SLD_INFO "QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1610565210"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name SLD_INFO "QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1725106627"
|
||
|
set_global_assignment -library "int_osc" -name MISC_FILE [file join $::quartus(qip_path) "../int_osc.cmp"]
|
||
|
set_global_assignment -library "int_osc" -name SLD_FILE [file join $::quartus(qip_path) "int_osc.debuginfo"]
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
|
||
| ... | ... | |
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_INTERNAL "Off"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MS4w"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYxMDU2NTIxMA==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTcyNTEwNjYyNw==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
|
||
|
set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||
| ... | ... | |
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_INTERNAL "Off"
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MjAuMQ=="
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MjMuMQ=="
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_DESCRIPTION "SW50ZXJuYWwgT3NjaWxsYXRvciBwcm92aWRlcyBpbnRlcm5hbCBjbG9jayBzb3VyY2UgZm9yIGRlYnVnZ2luZyBwdXJwb3NlLg=="
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "SU5GT1JNQVRJT04=::VGhlIG91dHB1dCBmcmVxdWVuY3kgZm9yIDEwTTAyLCAxME0wNCwgMTBNMDgsIDEwTTE2LCBhbmQgMTBNMjUgZGV2aWNlcyBpcyA1NX4xMTZNSHogPGJyPlRoZSBvdXRwdXQgZnJlcXVlbmN5IGZvciAxME00MCwgYW5kIDEwTTUwIGRldmljZXMgaXMgMzV+NzdNSHogPGJyPg==::SU5GT1JNQVRJT04="
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
|
||
| ... | ... | |
|
set_global_assignment -library "int_osc" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_int_osc.sdc"]
|
||
|
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_NAME "altera_int_osc"
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_VERSION "20.1"
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_VERSION "23.1"
|
||
|
set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_ENV "Qsys"
|
||
| atari_chips/pokeyv2/int_osc/synthesis/int_osc.vhd | ||
|---|---|---|
|
-- int_osc.vhd
|
||
|
|
||
|
-- Generated using ACDS version 20.1 720
|
||
|
-- Generated using ACDS version 23.1 993
|
||
|
|
||
|
library IEEE;
|
||
|
use IEEE.std_logic_1164.all;
|
||
| atari_chips/pokeyv2/int_osc/synthesis/submodules/altera_int_osc.sdc | ||
|---|---|---|
|
# (C) 2001-2020 Intel Corporation. All rights reserved.
|
||
|
# (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
# Your use of Intel Corporation's design tools, logic functions and other
|
||
|
# software and tools, and its AMPP partner logic functions, and any output
|
||
|
# files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/int_osc/synthesis/submodules/altera_int_osc.v | ||
|---|---|---|
|
// (C) 2001-2020 Intel Corporation. All rights reserved.
|
||
|
// (C) 2001-2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions and other
|
||
|
// software and tools, and its AMPP partner logic functions, and any output
|
||
|
// files from any of the foregoing (including device programming or simulation
|
||
| atari_chips/pokeyv2/int_osc.qsys | ||
|---|---|---|
|
<module
|
||
|
name="int_osc_0"
|
||
|
kind="altera_int_osc"
|
||
|
version="20.1"
|
||
|
version="23.1"
|
||
|
enabled="1"
|
||
|
autoexport="1">
|
||
|
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
|
||
| atari_chips/pokeyv2/int_osc.sopcinfo | ||
|---|---|---|
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
<EnsembleReport name="int_osc" kind="int_osc" version="1.0" fabric="QSYS">
|
||
|
<!-- Format version 20.1 720 (Future versions may contain additional information.) -->
|
||
|
<!-- 2021.01.13.20:13:30 -->
|
||
|
<!-- Format version 23.1 993 (Future versions may contain additional information.) -->
|
||
|
<!-- 2024.08.31.14:17:07 -->
|
||
|
<!-- A collection of modules and connections -->
|
||
|
<parameter name="AUTO_GENERATION_ID">
|
||
|
<type>java.lang.Integer</type>
|
||
|
<value>1610565210</value>
|
||
|
<value>1725106627</value>
|
||
|
<derived>false</derived>
|
||
|
<enabled>true</enabled>
|
||
|
<visible>false</visible>
|
||
| ... | ... | |
|
<module
|
||
|
name="int_osc_0"
|
||
|
kind="altera_int_osc"
|
||
|
version="20.1"
|
||
|
version="23.1"
|
||
|
path="int_osc_0">
|
||
|
<!-- Describes a single module. Module parameters are
|
||
|
the requested settings for a module instance. -->
|
||
| ... | ... | |
|
<visible>true</visible>
|
||
|
<valid>true</valid>
|
||
|
</parameter>
|
||
|
<interface name="oscena" kind="conduit_end" version="20.1">
|
||
|
<interface name="oscena" kind="conduit_end" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<role>oscena</role>
|
||
|
</port>
|
||
|
</interface>
|
||
|
<interface name="clkout" kind="clock_source" version="20.1">
|
||
|
<interface name="clkout" kind="clock_source" version="23.1">
|
||
|
<!-- The connection points exposed by a module instance for the
|
||
|
particular module parameters. Connection points and their
|
||
|
parameters are a RESULT of the module parameters. -->
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||
|
<displayName>Internal Oscillator</displayName>
|
||
|
<version>20.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Conduit</displayName>
|
||
|
<version>20.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<plugin>
|
||
|
<instanceCount>1</instanceCount>
|
||
| ... | ... | |
|
<type>com.altera.entityinterfaces.IElementClass</type>
|
||
|
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||
|
<displayName>Clock Output</displayName>
|
||
|
<version>20.1</version>
|
||
|
<version>23.1</version>
|
||
|
</plugin>
|
||
|
<reportVersion>20.1 720</reportVersion>
|
||
|
<reportVersion>23.1 993</reportVersion>
|
||
|
<uniqueIdentifier></uniqueIdentifier>
|
||
|
</EnsembleReport>
|
||
Also available in: Unified diff
ip upgrade to q23