Revision 1425
Added by markw 11 months ago
| atari_chips/pokeyv2/lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v | ||
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//lpm_ff CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" LPM_WIDTH=1 clock data q
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//VERSION_BEGIN 20.1 cbx_lpm_ff 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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//synthesis_resources = lut 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_soft_lvds_rx_twD2Tqf3
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(
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clock,
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data,
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q) /* synthesis synthesis_clearbox=1 */;
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input clock;
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input [0:0] data;
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output [0:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [0:0] data;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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reg [0:0] ff_dffe;
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wire enable;
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// synopsys translate_off
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initial
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ff_dffe = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (enable == 1'b1) ff_dffe <= data;
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assign
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enable = 1'b1,
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q = ff_dffe;
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endmodule //altera_soft_lvds_rx_twD2Tqf3
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//VALID FILE
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| atari_chips/pokeyv2/lvds_tx/altera_soft_lvds_tx_twD5CSXW.v | ||
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//altlvds_tx CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" COMMON_RX_TX_PLL="OFF" CORECLOCK_DIVIDE_BY=2 DATA_RATE="720.0 Mbps" DESERIALIZATION_FACTOR=1 DEVICE_FAMILY="MAX 10" DIFFERENTIAL_DRIVE=0 ENABLE_CLK_LATENCY="OFF" IMPLEMENT_IN_LES="ON" INCLOCK_BOOST=0 INCLOCK_DATA_ALIGNMENT="EDGE_ALIGNED" INCLOCK_PERIOD=5000 INCLOCK_PHASE_SHIFT=0 MULTI_CLOCK="OFF" NUMBER_OF_CHANNELS=1 OUTCLOCK_ALIGNMENT="EDGE_ALIGNED" OUTCLOCK_DIVIDE_BY=1 OUTCLOCK_DUTY_CYCLE=50 OUTCLOCK_MULTIPLY_BY=1 OUTCLOCK_PHASE_SHIFT=0 OUTCLOCK_RESOURCE="AUTO" OUTPUT_DATA_RATE=720 PLL_COMPENSATION_MODE="AUTO" PLL_SELF_RESET_ON_LOSS_LOCK="OFF" PREEMPHASIS_SETTING=0 REGISTERED_INPUT="OFF" USE_EXTERNAL_PLL="OFF" USE_NO_PHASE_SHIFT="ON" VOD_SETTING=0 tx_in tx_inclock tx_out CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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//VERSION_BEGIN 20.1 cbx_altaccumulate 2020:11:11:17:03:37:SJ cbx_altclkbuf 2020:11:11:17:03:37:SJ cbx_altddio_in 2020:11:11:17:03:37:SJ cbx_altddio_out 2020:11:11:17:03:37:SJ cbx_altera_syncram_nd_impl 2020:11:11:17:03:37:SJ cbx_altiobuf_bidir 2020:11:11:17:03:37:SJ cbx_altiobuf_in 2020:11:11:17:03:37:SJ cbx_altiobuf_out 2020:11:11:17:03:37:SJ cbx_altlvds_tx 2020:11:11:17:03:37:SJ cbx_altpll 2020:11:11:17:03:37:SJ cbx_altsyncram 2020:11:11:17:03:37:SJ cbx_arriav 2020:11:11:17:03:36:SJ cbx_cyclone 2020:11:11:17:03:37:SJ cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_compare 2020:11:11:17:03:37:SJ cbx_lpm_counter 2020:11:11:17:03:37:SJ cbx_lpm_decode 2020:11:11:17:03:37:SJ cbx_lpm_mux 2020:11:11:17:03:37:SJ cbx_lpm_shiftreg 2020:11:11:17:03:37:SJ cbx_maxii 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_stratixiii 2020:11:11:17:03:37:SJ cbx_stratixv 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
|
||
|
// and other software and tools, and any partner logic
|
||
|
// functions, and any output files from any of the foregoing
|
||
|
// (including device programming or simulation files), and any
|
||
|
// associated documentation or information are expressly subject
|
||
|
// to the terms and conditions of the Intel Program License
|
||
|
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
// the Intel FPGA IP License Agreement, or other applicable license
|
||
|
// agreement, including, without limitation, that your use is for
|
||
|
// the sole purpose of programming logic devices manufactured by
|
||
|
// Intel and sold by Intel or its authorized distributors. Please
|
||
|
// refer to the applicable agreement for further details, at
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||
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// https://fpgasoftware.intel.com/eula.
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//synthesis_resources =
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_soft_lvds_tx_twD5CSXW
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(
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tx_in,
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tx_inclock,
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tx_out) /* synthesis synthesis_clearbox=1 */;
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input [0:0] tx_in;
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input tx_inclock;
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output [0:0] tx_out;
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wire [0:0] tx_out_wire;
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assign
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tx_out = tx_out_wire,
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tx_out_wire = tx_in;
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endmodule //altera_soft_lvds_tx_twD5CSXW
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//VALID FILE
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| atari_chips/pokeyv2/lvds_rx/altera_soft_lvds_rx_uCmNW05P.v | ||
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//lpm_ff CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" LPM_WIDTH=1 clock data q
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//VERSION_BEGIN 23.1 cbx_lpm_ff 2024:05:14:17:53:42:SC cbx_mgl 2024:05:14:18:00:13:SC VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions
|
||
|
// and other software and tools, and any partner logic
|
||
|
// functions, and any output files from any of the foregoing
|
||
|
// (including device programming or simulation files), and any
|
||
|
// associated documentation or information are expressly subject
|
||
|
// to the terms and conditions of the Intel Program License
|
||
|
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
// the Intel FPGA IP License Agreement, or other applicable license
|
||
|
// agreement, including, without limitation, that your use is for
|
||
|
// the sole purpose of programming logic devices manufactured by
|
||
|
// Intel and sold by Intel or its authorized distributors. Please
|
||
|
// refer to the applicable agreement for further details, at
|
||
|
// https://fpgasoftware.intel.com/eula.
|
||
|
|
||
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//synthesis_resources = lut 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_soft_lvds_rx_uCmNW05P
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(
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clock,
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data,
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q) /* synthesis synthesis_clearbox=1 */;
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input clock;
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input [0:0] data;
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output [0:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [0:0] data;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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reg [0:0] ff_dffe;
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wire enable;
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// synopsys translate_off
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initial
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ff_dffe = 0;
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// synopsys translate_on
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always @ ( posedge clock)
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if (enable == 1'b1) ff_dffe <= data;
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assign
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enable = 1'b1,
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q = ff_dffe;
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endmodule //altera_soft_lvds_rx_uCmNW05P
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//VALID FILE
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| atari_chips/pokeyv2/lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v | ||
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//altlvds_tx CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" COMMON_RX_TX_PLL="OFF" CORECLOCK_DIVIDE_BY=2 DATA_RATE="720.0 Mbps" DESERIALIZATION_FACTOR=1 DEVICE_FAMILY="MAX 10" DIFFERENTIAL_DRIVE=0 ENABLE_CLK_LATENCY="OFF" IMPLEMENT_IN_LES="ON" INCLOCK_BOOST=0 INCLOCK_DATA_ALIGNMENT="EDGE_ALIGNED" INCLOCK_PERIOD=5000 INCLOCK_PHASE_SHIFT=0 MULTI_CLOCK="OFF" NUMBER_OF_CHANNELS=1 OUTCLOCK_ALIGNMENT="EDGE_ALIGNED" OUTCLOCK_DIVIDE_BY=1 OUTCLOCK_DUTY_CYCLE=50 OUTCLOCK_MULTIPLY_BY=1 OUTCLOCK_PHASE_SHIFT=0 OUTCLOCK_RESOURCE="AUTO" OUTPUT_DATA_RATE=720 PLL_COMPENSATION_MODE="AUTO" PLL_SELF_RESET_ON_LOSS_LOCK="OFF" PREEMPHASIS_SETTING=0 REGISTERED_INPUT="OFF" USE_EXTERNAL_PLL="OFF" USE_NO_PHASE_SHIFT="ON" VOD_SETTING=0 tx_in tx_inclock tx_out CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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//VERSION_BEGIN 23.1 cbx_altaccumulate 2024:05:14:17:53:42:SC cbx_altclkbuf 2024:05:14:17:53:42:SC cbx_altddio_in 2024:05:14:17:53:42:SC cbx_altddio_out 2024:05:14:17:53:42:SC cbx_altera_syncram_nd_impl 2024:05:14:17:53:42:SC cbx_altiobuf_bidir 2024:05:14:17:53:42:SC cbx_altiobuf_in 2024:05:14:17:53:42:SC cbx_altiobuf_out 2024:05:14:17:53:42:SC cbx_altlvds_tx 2024:05:14:17:53:42:SC cbx_altpll 2024:05:14:17:53:42:SC cbx_altsyncram 2024:05:14:17:53:42:SC cbx_arriav 2024:05:14:17:53:42:SC cbx_cyclone 2024:05:14:17:53:42:SC cbx_cycloneii 2024:05:14:17:53:42:SC cbx_lpm_add_sub 2024:05:14:17:53:42:SC cbx_lpm_compare 2024:05:14:17:53:42:SC cbx_lpm_counter 2024:05:14:17:53:42:SC cbx_lpm_decode 2024:05:14:17:53:42:SC cbx_lpm_mux 2024:05:14:17:53:42:SC cbx_lpm_shiftreg 2024:05:14:17:53:42:SC cbx_maxii 2024:05:14:17:53:42:SC cbx_mgl 2024:05:14:18:00:13:SC cbx_nadder 2024:05:14:17:53:42:SC cbx_stratix 2024:05:14:17:53:42:SC cbx_stratixii 2024:05:14:17:53:42:SC cbx_stratixiii 2024:05:14:17:53:42:SC cbx_stratixv 2024:05:14:17:53:42:SC cbx_util_mgl 2024:05:14:17:53:42:SC VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// Copyright (C) 2024 Intel Corporation. All rights reserved.
|
||
|
// Your use of Intel Corporation's design tools, logic functions
|
||
|
// and other software and tools, and any partner logic
|
||
|
// functions, and any output files from any of the foregoing
|
||
|
// (including device programming or simulation files), and any
|
||
|
// associated documentation or information are expressly subject
|
||
|
// to the terms and conditions of the Intel Program License
|
||
|
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
// the Intel FPGA IP License Agreement, or other applicable license
|
||
|
// agreement, including, without limitation, that your use is for
|
||
|
// the sole purpose of programming logic devices manufactured by
|
||
|
// Intel and sold by Intel or its authorized distributors. Please
|
||
|
// refer to the applicable agreement for further details, at
|
||
|
// https://fpgasoftware.intel.com/eula.
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||
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//synthesis_resources =
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module altera_soft_lvds_tx_uCmMXfGB
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(
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tx_in,
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tx_inclock,
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tx_out) /* synthesis synthesis_clearbox=1 */;
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input [0:0] tx_in;
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input tx_inclock;
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output [0:0] tx_out;
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wire [0:0] tx_out_wire;
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assign
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tx_out = tx_out_wire,
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tx_out_wire = tx_in;
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endmodule //altera_soft_lvds_tx_uCmMXfGB
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//VALID FILE
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Also available in: Unified diff
Rest of ip upgrade to q23