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-- https://ackspace.nl/wiki/SP/DIF_transmitter_project
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-- (c) Danny Witberg
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity spdif_transmitter is
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port(
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bit_clock : in std_logic; -- 128x Fsample (6.144MHz for 48K samplerate)
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data_in : in std_logic_vector(23 downto 0);
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address_out : out std_logic := '0'; -- 1 address bit means stereo only
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spdif_out : out std_logic
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);
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end entity spdif_transmitter;
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architecture behavioral of spdif_transmitter is
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signal data_in_buffer : std_logic_vector(23 downto 0);
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signal bit_counter : std_logic_vector(5 downto 0) := (others => '0');
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signal frame_counter : std_logic_vector(8 downto 0) := (others => '0');
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signal data_biphase : std_logic := '0';
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signal data_out_buffer : std_logic_vector(7 downto 0);
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signal parity : std_logic;
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signal channel_status_shift : std_logic_vector(23 downto 0);
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signal channel_status : std_logic_vector(23 downto 0) := "001000000000000001000000";
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begin
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bit_clock_counter : process (bit_clock)
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begin
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if bit_clock'event and bit_clock = '1' then
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bit_counter <= bit_counter + 1;
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end if;
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end process bit_clock_counter;
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data_latch : process (bit_clock)
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begin
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if bit_clock'event and bit_clock = '1' then
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parity <= data_in_buffer(23) xor data_in_buffer(22) xor data_in_buffer(21) xor data_in_buffer(20) xor data_in_buffer(19) xor data_in_buffer(18) xor data_in_buffer(17) xor data_in_buffer(16) xor data_in_buffer(15) xor data_in_buffer(14) xor data_in_buffer(13) xor data_in_buffer(12) xor data_in_buffer(11) xor data_in_buffer(10) xor data_in_buffer(9) xor data_in_buffer(8) xor data_in_buffer(7) xor data_in_buffer(6) xor data_in_buffer(5) xor data_in_buffer(4) xor data_in_buffer(3) xor data_in_buffer(2) xor data_in_buffer(1) xor data_in_buffer(0) xor channel_status_shift(23);
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if bit_counter = "000011" then
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data_in_buffer <= data_in;
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end if;
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if bit_counter = "111111" then
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if frame_counter = "101111111" then
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frame_counter <= (others => '0');
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else
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frame_counter <= frame_counter + 1;
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end if;
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end if;
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end if;
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end process data_latch;
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data_output : process (bit_clock)
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begin
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if bit_clock'event and bit_clock = '1' then
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if bit_counter = "111111" then
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if frame_counter = "101111111" then -- next frame is 0, load preamble Z
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address_out <= '0';
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channel_status_shift <= channel_status;
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data_out_buffer <= "10011100";
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else
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if frame_counter(0) = '1' then -- next frame is even, load preamble X
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channel_status_shift <= channel_status_shift(22 downto 0) & '0';
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data_out_buffer <= "10010011";
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address_out <= '0';
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else -- next frame is odd, load preable Y
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data_out_buffer <= "10010110";
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address_out <= '1';
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end if;
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end if;
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else
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if bit_counter(2 downto 0) = "111" then -- load new part of data into buffer
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case bit_counter(5 downto 3) is
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when "000" =>
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data_out_buffer <= '1' & data_in_buffer(0) & '1' & data_in_buffer(1) & '1' & data_in_buffer(2) & '1' & data_in_buffer(3);
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when "001" =>
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data_out_buffer <= '1' & data_in_buffer(4) & '1' & data_in_buffer(5) & '1' & data_in_buffer(6) & '1' & data_in_buffer(7);
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when "010" =>
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data_out_buffer <= '1' & data_in_buffer(8) & '1' & data_in_buffer(9) & '1' & data_in_buffer(10) & '1' & data_in_buffer(11);
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when "011" =>
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data_out_buffer <= '1' & data_in_buffer(12) & '1' & data_in_buffer(13) & '1' & data_in_buffer(14) & '1' & data_in_buffer(15);
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when "100" =>
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data_out_buffer <= '1' & data_in_buffer(16) & '1' & data_in_buffer(17) & '1' & data_in_buffer(18) & '1' & data_in_buffer(19);
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when "101" =>
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data_out_buffer <= '1' & data_in_buffer(20) & '1' & data_in_buffer(21) & '1' & data_in_buffer(22) & '1' & data_in_buffer(23);
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when "110" =>
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data_out_buffer <= "10101" & channel_status_shift(23) & "1" & parity;
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when others =>
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end case;
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else
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data_out_buffer <= data_out_buffer(6 downto 0) & '0';
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end if;
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end if;
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end if;
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end process data_output;
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biphaser : process (bit_clock)
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begin
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if bit_clock'event and bit_clock = '1' then
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if data_out_buffer(data_out_buffer'left) = '1' then
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data_biphase <= not data_biphase;
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end if;
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end if;
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end process biphaser;
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spdif_out <= data_biphase;
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end behavioral;
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