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-- megafunction wizard: %GPIO Lite Intel FPGA IP v20.1%
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-- GENERATION: XML
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-- paddle_gpio.vhd
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-- Generated using ACDS version 20.1 720
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity paddle_gpio is
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port (
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dout : out std_logic_vector(7 downto 0); -- dout.export
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din : in std_logic_vector(7 downto 0) := (others => '0'); -- din.export
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pad_io : inout std_logic_vector(7 downto 0) := (others => '0'); -- pad_io.export
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pad_io_b : inout std_logic_vector(7 downto 0) := (others => '0'); -- pad_io_b.export
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oe : in std_logic_vector(7 downto 0) := (others => '0') -- oe.export
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);
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end entity paddle_gpio;
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architecture rtl of paddle_gpio is
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component altera_gpio_lite is
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generic (
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PIN_TYPE : string := "output";
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SIZE : integer := 4;
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REGISTER_MODE : string := "bypass";
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BUFFER_TYPE : string := "single-ended";
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ASYNC_MODE : string := "none";
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SYNC_MODE : string := "none";
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BUS_HOLD : string := "false";
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OPEN_DRAIN_OUTPUT : string := "false";
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ENABLE_OE_PORT : string := "false";
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ENABLE_NSLEEP_PORT : string := "false";
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ENABLE_CLOCK_ENA_PORT : string := "false";
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SET_REGISTER_OUTPUTS_HIGH : string := "false";
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INVERT_OUTPUT : string := "false";
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INVERT_INPUT_CLOCK : string := "false";
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USE_ONE_REG_TO_DRIVE_OE : string := "false";
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USE_DDIO_REG_TO_DRIVE_OE : string := "false";
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USE_ADVANCED_DDR_FEATURES : string := "false";
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USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY : string := "false";
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ENABLE_OE_HALF_CYCLE_DELAY : string := "true";
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INVERT_CLKDIV_INPUT_CLOCK : string := "false";
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ENABLE_PHASE_INVERT_CTRL_PORT : string := "false";
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ENABLE_HR_CLOCK : string := "false";
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INVERT_OUTPUT_CLOCK : string := "false";
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INVERT_OE_INCLOCK : string := "false";
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ENABLE_PHASE_DETECTOR_FOR_CK : string := "false"
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);
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port (
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dout : out std_logic_vector(7 downto 0); -- export
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din : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
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pad_io : inout std_logic_vector(7 downto 0) := (others => 'X'); -- export
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pad_io_b : inout std_logic_vector(7 downto 0) := (others => 'X'); -- export
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oe : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
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inclocken : in std_logic := 'X'; -- export
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outclocken : in std_logic := 'X'; -- export
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inclock : in std_logic := 'X'; -- export
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fr_clock : out std_logic_vector(7 downto 0); -- export
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hr_clock : out std_logic; -- export
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invert_hr_clock : in std_logic := 'X'; -- export
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outclock : in std_logic := 'X'; -- export
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phy_mem_clock : in std_logic := 'X'; -- export
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mimic_clock : out std_logic_vector(7 downto 0); -- export
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pad_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
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pad_in_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
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pad_out : out std_logic_vector(7 downto 0); -- export
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pad_out_b : out std_logic_vector(7 downto 0); -- export
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aset : in std_logic := 'X'; -- export
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aclr : in std_logic := 'X'; -- export
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sclr : in std_logic := 'X'; -- export
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nsleep : in std_logic_vector(7 downto 0) := (others => 'X') -- export
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);
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end component altera_gpio_lite;
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begin
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paddle_gpio_inst : component altera_gpio_lite
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generic map (
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PIN_TYPE => "bidir",
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SIZE => 8,
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REGISTER_MODE => "bypass",
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BUFFER_TYPE => "pseudo_differential",
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ASYNC_MODE => "none",
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SYNC_MODE => "none",
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BUS_HOLD => "false",
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OPEN_DRAIN_OUTPUT => "false",
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ENABLE_OE_PORT => "true",
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ENABLE_NSLEEP_PORT => "false",
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ENABLE_CLOCK_ENA_PORT => "false",
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SET_REGISTER_OUTPUTS_HIGH => "false",
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INVERT_OUTPUT => "false",
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INVERT_INPUT_CLOCK => "false",
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USE_ONE_REG_TO_DRIVE_OE => "false",
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USE_DDIO_REG_TO_DRIVE_OE => "false",
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USE_ADVANCED_DDR_FEATURES => "false",
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USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",
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ENABLE_OE_HALF_CYCLE_DELAY => "true",
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INVERT_CLKDIV_INPUT_CLOCK => "false",
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ENABLE_PHASE_INVERT_CTRL_PORT => "false",
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ENABLE_HR_CLOCK => "false",
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INVERT_OUTPUT_CLOCK => "false",
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INVERT_OE_INCLOCK => "false",
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ENABLE_PHASE_DETECTOR_FOR_CK => "false"
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)
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port map (
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dout => dout, -- dout.export
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din => din, -- din.export
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pad_io => pad_io, -- pad_io.export
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pad_io_b => pad_io_b, -- pad_io_b.export
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oe => oe, -- oe.export
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inclocken => '1', -- (terminated)
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outclocken => '1', -- (terminated)
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inclock => '0', -- (terminated)
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fr_clock => open, -- (terminated)
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hr_clock => open, -- (terminated)
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invert_hr_clock => '0', -- (terminated)
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outclock => '0', -- (terminated)
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phy_mem_clock => '0', -- (terminated)
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mimic_clock => open, -- (terminated)
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pad_in => "00000000", -- (terminated)
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pad_in_b => "00000000", -- (terminated)
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pad_out => open, -- (terminated)
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pad_out_b => open, -- (terminated)
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aset => '0', -- (terminated)
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aclr => '0', -- (terminated)
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sclr => '0', -- (terminated)
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nsleep => "00000000" -- (terminated)
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);
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end architecture rtl; -- of paddle_gpio
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-- Retrieval info: <?xml version="1.0"?>
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--<!--
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-- Generated by Altera MegaWizard Launcher Utility version 1.0
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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-- ************************************************************
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-- Copyright (C) 1991-2024 Altera Corporation
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-- Any megafunction design, and related net list (encrypted or decrypted),
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-- support information, device programming or simulation file, and any other
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-- associated documentation or information provided by Altera or a partner
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-- under Altera's Megafunction Partnership Program may be used only to
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-- program PLD devices (but not masked PLD devices) from Altera. Any other
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-- use of such megafunction design, net list, support information, device
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-- programming or simulation file, or any other related documentation or
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-- information is prohibited for any other purpose, including, but not
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-- limited to modification, reverse engineering, de-compiling, or use with
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-- any other silicon devices, unless such use is explicitly licensed under
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-- a separate agreement with Altera or a megafunction partner. Title to
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-- the intellectual property, including patents, copyrights, trademarks,
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-- trade secrets, or maskworks, embodied in any such megafunction design,
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-- net list, support information, device programming or simulation file, or
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-- any other related documentation or information provided by Altera or a
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-- megafunction partner, remains with Altera, the megafunction partner, or
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-- their respective licensors. No other licenses, including any licenses
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-- needed under any third party's intellectual property, are provided herein.
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---->
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-- Retrieval info: <instance entity-name="altera_gpio_lite" version="20.1" >
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-- Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
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-- Retrieval info: <generic name="PIN_TYPE" value="bidir" />
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-- Retrieval info: <generic name="SIZE" value="8" />
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-- Retrieval info: <generic name="gui_true_diff_buf" value="false" />
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-- Retrieval info: <generic name="gui_pseudo_diff_buf" value="true" />
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-- Retrieval info: <generic name="gui_bus_hold" value="false" />
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-- Retrieval info: <generic name="gui_open_drain" value="false" />
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-- Retrieval info: <generic name="gui_enable_oe_port" value="false" />
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-- Retrieval info: <generic name="gui_enable_nsleep_port" value="false" />
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-- Retrieval info: <generic name="gui_io_reg_mode" value="bypass" />
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-- Retrieval info: <generic name="gui_enable_aclr_port" value="false" />
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-- Retrieval info: <generic name="gui_enable_aset_port" value="false" />
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-- Retrieval info: <generic name="gui_enable_sclr_port" value="false" />
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-- Retrieval info: <generic name="gui_set_registers_to_power_up_high" value="false" />
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-- Retrieval info: <generic name="gui_clock_enable" value="false" />
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-- Retrieval info: <generic name="gui_invert_output" value="false" />
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-- Retrieval info: <generic name="gui_invert_input_clock" value="false" />
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-- Retrieval info: <generic name="gui_use_register_to_drive_obuf_oe" value="false" />
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-- Retrieval info: <generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
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-- Retrieval info: <generic name="gui_use_advanced_ddr_features" value="false" />
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-- Retrieval info: <generic name="gui_enable_phase_detector_for_ck" value="false" />
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-- Retrieval info: <generic name="gui_enable_oe_half_cycle_delay" value="true" />
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-- Retrieval info: <generic name="gui_enable_hr_clock" value="false" />
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-- Retrieval info: <generic name="gui_enable_invert_hr_clock_port" value="false" />
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-- Retrieval info: <generic name="gui_invert_clkdiv_input_clock" value="false" />
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-- Retrieval info: <generic name="gui_invert_output_clock" value="false" />
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-- Retrieval info: <generic name="gui_invert_oe_inclock" value="false" />
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-- Retrieval info: <generic name="gui_use_hardened_ddio_input_registers" value="false" />
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-- Retrieval info: </instance>
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-- IPFS_FILES : paddle_gpio.vho
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-- RELATED_FILES: paddle_gpio.vhd, altera_gpio_lite.sv
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