Revision 1414
Added by markw 12 months ago
| atari_chips/pokeyv2/SID/f_distortion.vhdl | ||
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signal yadj_reg : unsigned(25 downto 0);
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signal ychpos : unsigned(12 downto 0);
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signal f_distorted_next : unsigned(12 downto 0);
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signal STATE_next : SIGNED(17 downto 8);
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signal STATE_reg : SIGNED(17 downto 8);
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signal F_RAW_next : UNSIGNED(12 downto 0);
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signal F_RAW_reg : UNSIGNED(12 downto 0);
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begin
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-- register
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process(clk,reset_n)
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| ... | ... | |
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if (reset_n='0') then
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y1_reg <= (others=>'0');
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yadj_reg <= (others=>'0');
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state_reg <= (others=>'0');
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f_raw_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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y1_reg <= y1;
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yadj_reg <= yadj_next;
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state_reg <= state_next;
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f_raw_reg <= f_raw_next;
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end if;
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end process;
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process (state,f_raw, y1, y2, ych, ychpos, y1_reg, yadj_reg)
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state_next <= state;
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f_raw_next <= f_raw;
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process (state_reg,f_raw_reg, y1, y2, ych, ychpos, y1_reg, yadj_reg)
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type LOOKUP_TYPE is array (0 to 38) of unsigned(12 downto 0);
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variable lookup : LOOKUP_TYPE;
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| ... | ... | |
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begin
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-- assumption: /home/markw/fpga/svn/jsidplay2-code/jsidplay2/src/main/java/builder/resid/residfp/Filter6581.java
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pos := (others=>'0');
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if (state(17)='0') then
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pos := unsigned('0'&state(16 downto 8)&"000"&"0") + resize('0'&f_raw,14);
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if (state_reg(17)='0') then
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pos := unsigned('0'&state_reg(16 downto 8)&"000"&"0") + resize('0'&f_raw_reg,14);
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end if;
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if (pos(18 downto 12) > to_unsigned(37,6)) then
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pos(18) := '0';
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Also available in: Unified diff
Improving timing by registering on the input