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Revision 1406

Added by markw over 1 year ago

Improve phi timing. Try to improve RDY timing.

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atari_chips/sally/sallymax.vhd
signal CPU_NMI_N : std_logic;
signal CPU_IRQ_N : std_logic;
signal CPU_RDY : std_logic;
signal BUS_ADDR : std_logic_vector(15 downto 0);
signal BUS_ADDR_OE : std_logic;
signal BUS_DATA : std_logic_vector(7 downto 0);
......
CPU_REQUEST_COMPLETE => CPU_REQUEST_COMPLETE,
CPU_NMI_N => CPU_NMI_N,
CPU_IRQ_N => CPU_IRQ_N,
CPU_RDY => CPU_RDY,
-- bus side
BUS_DATA_IN => D,
......
BUS_DATA_OUT => BUS_DATA,
BUS_DATA_OE => BUS_DATA_OE,
BUS_WRITE_N => BUS_WRITE_N,
BUS_WRITE_OE => BUS_WRITE_OE
BUS_WRITE_OE => BUS_WRITE_OE,
BUS_RDY => RDY
);
cpu6502 : entity work.cpu
......
NMI_n => CPU_NMI_N,
MEMORY_READY => CPU_REQUEST_COMPLETE,
THROTTLE => CPU_REQUEST,
RDY => RDY,
RDY => CPU_RDY,
DI => CPU_READ_DATA,
R_W_n => CPU_WRITE_N,
CPU_FETCH => open,
atari_chips/sally/timing6502.vhd
CPU_IRQ_N : OUT STD_LOGIC;
CPU_NMI_N : OUT STD_LOGIC;
CPU_RDY : OUT STD_LOGIC;
-- 6502 side
BUS_DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
BUS_RDY : IN STD_LOGIC;
BUS_PHI1 : OUT STD_LOGIC;
BUS_PHI2 : OUT STD_LOGIC;
......
signal NMI_N_REG : std_logic;
signal IRQ_N_NEXT : std_logic;
signal IRQ_N_REG : std_logic;
signal RDY_NEXT : std_logic;
signal RDY_REG : std_logic;
signal HALT_N_NEXT : std_logic;
signal HALT_N_REG : std_logic;
......
IRQ_N_REG <= '1';
NMI_N_REG <= '1';
HALT_N_REG <= '1';
RDY_REG <= '1';
init_reg <= (others=>'0');
elsif (clk'event and clk='1') then
state_reg <= state_next;
......
IRQ_N_REG <= IRQ_N_NEXT;
NMI_N_REG <= NMI_N_NEXT;
HALT_N_REG <= HALT_N_NEXT;
RDY_REG <= RDY_NEXT;
init_reg <= init_next;
end if;
......
end process;
-- next state
process(initmode, syncphi2, state_reg, phi1_reg, phi2_reg, addr_in, data_in, addr_reg, addr_oe_reg, data_reg, data_oe_reg, data_read_reg, bus_data_in, write_n_reg, write_in, request_handling_reg, write_oe_reg, irq_n_reg, nmi_n_reg, halt_n_reg, nmi_n, irq_n, halt_n)
process(initmode, syncphi2, state_reg, phi1_reg, phi2_reg, addr_in, data_in, addr_reg, addr_oe_reg, data_reg, data_oe_reg, data_read_reg, bus_data_in, write_n_reg, write_in, request_handling_reg, write_oe_reg, irq_n_reg, nmi_n_reg, halt_n_reg, bus_rdy, rdy_reg, nmi_n, irq_n, halt_n)
begin
CPU_REQUEST_COMPLETE <= '0';
......
irq_n_next <= irq_n_reg;
nmi_n_next <= nmi_n_reg;
halt_n_next <= halt_n_reg;
rdy_next <= rdy_reg;
if (initmode = '0') then
state_next <= std_logic_vector(unsigned(state_reg)+1);
end if;
if (syncphi2 = '1') then
phi1_next <= '0';
state_next <= "01110";
phi1_next <= '1';
state_next <= "01111";
end if;
rdy_next <= bus_rdy;
case state_reg is
when "00000" =>
......
CPU_REQUEST <= request_handling_reg;
CPU_NMI_N <= NMI_N_REG;
CPU_IRQ_N <= IRQ_N_REG;
CPU_RDY <= RDY_REG;
END vhdl;

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