Revision 1378
Added by markw over 1 year ago
| common/zpu/sio_handler.vhdl | ||
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signal addr_decoded : std_logic_vector(15 downto 0);
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signal receive_enable : std_logic;
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signal receive_detect : std_logic;
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signal transmit_enable : std_logic;
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signal fifo_tx_write : std_logic;
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| ... | ... | |
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end process;
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process(pokey_enable,receive_enable,receive_divisor_reg,receive_divisor_count_reg)
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process(pokey_enable,receive_enable,receive_detect,receive_divisor_reg,receive_divisor_count_reg)
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begin
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receive_divisor_next <= receive_divisor_reg;
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receive_divisor_count_next <= receive_divisor_count_reg;
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| ... | ... | |
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end if;
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if (receive_enable='1') then
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receive_divisor_next <= receive_divisor_count_reg;
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receive_divisor_count_next <= (others=>'0');
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end if;
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if (receive_enable='1' and receive_detect='1') then
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receive_divisor_next <= receive_divisor_count_reg;
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end if;
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end process;
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-- Transmit fifo (7-0= data)
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| ... | ... | |
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s2p_start <= '0';
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s2p_write <= '0';
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receive_detect <= '0';
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if (framing_error_clear='1') then
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s2p_framing_error_next <= '0';
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| ... | ... | |
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s2p_start <= '1';
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end if;
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when S2P_STATE_SHIFT_0 =>
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receive_detect <= '1';
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s2p_state_next <= S2P_STATE_SHIFT_1;
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when S2P_STATE_SHIFT_1 =>
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receive_detect <= '1';
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s2p_state_next <= S2P_STATE_SHIFT_2;
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when S2P_STATE_SHIFT_2 =>
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receive_detect <= '1';
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s2p_state_next <= S2P_STATE_SHIFT_3;
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when S2P_STATE_SHIFT_3 =>
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s2p_state_next <= S2P_STATE_SHIFT_4;
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Also available in: Unified diff
Only poll clock at sensible times