Project

General

Profile

« Previous | Next » 

Revision 1337

Added by markw about 4 years ago

Reviewed remaining sdc files

View differences:

atari_chips/pokeyv2/pokeymaxv1.sdc
create_clock -period 1.9MHz [get_ports PHI2]
create_clock -period 87.36MHz [get_ports CLK_SLOW]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous \
-group { PHI2 } \
-group { CLK_SLOW } \
-group { \
pll_inst|altpll_component|auto_generated|pll1|clk[0] \
pll_inst|altpll_component|auto_generated|pll1|clk[1] \
}
# IOX_RST : OUT STD_LOGIC;
# IOX_INT : IN STD_LOGIC;
# IOX_SDA : INOUT STD_LOGIC;
# IOX_SCL : INOUT STD_LOGIC
#create_clock -period 56.67MHz -name cart_clk
#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
#
atari_chips/pokeyv2/build.sh
my $type = $variants{$variant}->{"type"};
my $board = $variants{$variant}->{"board"};
my $bus = $variants{$variant}->{"bus"};
my $flash = $variants{$variant}->{"enable_flash"};
my $noflash = "";
if (not defined $flash or $flash eq "0") {$noflash = "_noflash"};
my $dir = "build_$variant";
my $dir = "build_$variant";
`rm -rf $dir`;
mkdir $dir;
`cp *.vhd* $dir`;
......
`cp slave_timing_6502$bus.vhd $dir/slave_timing_6502.vhd`;
`cp swapbits $dir`;
`cp $type$board.sdc $dir/$type.sdc`;
`cp $type$board$noflash.sdc $dir/$type.sdc`;
`cp $type*.qpf $dir`;
`cp -r int_osc* $dir`;
`cp -r pll* $dir`;
atari_chips/pokeyv2/pokeymax.sdc
-group { CLK_SLOW } \
-group { \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc } \
-group { \
pll_inst|altpll_component|auto_generated|pll1|clk[0] \
pll_inst|altpll_component|auto_generated|pll1|clk[1] \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
} \
-group { \
pll_inst|altpll_component|auto_generated|pll1|clk[2] \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
}
# IOX_RST : OUT STD_LOGIC;
atari_chips/pokeyv2/pokeymax_noflash.sdc
create_clock -period 1.9MHz [get_ports PHI2]
create_clock -period 87.36MHz [get_ports CLK_SLOW]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous \
-group { PHI2 } \
-group { CLK_SLOW } \
-group { \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
} \
-group { \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
}
# IOX_RST : OUT STD_LOGIC;
# IOX_INT : IN STD_LOGIC;
# IOX_SDA : INOUT STD_LOGIC;
# IOX_SCL : INOUT STD_LOGIC
#create_clock -period 56.67MHz -name cart_clk
#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
#
atari_chips/pokeyv2/pokeymaxv1_noflash.sdc
create_clock -period 1.9MHz [get_ports PHI2]
create_clock -period 87.36MHz [get_ports CLK_SLOW]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous \
-group { PHI2 } \
-group { CLK_SLOW } \
-group { \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
} \
-group { \
\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
}
# IOX_RST : OUT STD_LOGIC;
# IOX_INT : IN STD_LOGIC;
# IOX_SDA : INOUT STD_LOGIC;
# IOX_SCL : INOUT STD_LOGIC
#create_clock -period 56.67MHz -name cart_clk
#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
#
#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
#
#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
#

Also available in: Unified diff