Revision 1337
Added by markw almost 4 years ago
atari_chips/pokeyv2/pokeymaxv1.sdc | ||
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create_clock -period 1.9MHz [get_ports PHI2]
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create_clock -period 87.36MHz [get_ports CLK_SLOW]
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derive_pll_clocks
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derive_clock_uncertainty
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set_clock_groups -asynchronous \
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-group { PHI2 } \
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-group { CLK_SLOW } \
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-group { \
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pll_inst|altpll_component|auto_generated|pll1|clk[0] \
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pll_inst|altpll_component|auto_generated|pll1|clk[1] \
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}
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# IOX_RST : OUT STD_LOGIC;
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# IOX_INT : IN STD_LOGIC;
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# IOX_SDA : INOUT STD_LOGIC;
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# IOX_SCL : INOUT STD_LOGIC
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#create_clock -period 56.67MHz -name cart_clk
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#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
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#
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atari_chips/pokeyv2/build.sh | ||
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my $type = $variants{$variant}->{"type"};
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my $board = $variants{$variant}->{"board"};
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my $bus = $variants{$variant}->{"bus"};
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my $flash = $variants{$variant}->{"enable_flash"};
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my $noflash = "";
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if (not defined $flash or $flash eq "0") {$noflash = "_noflash"};
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my $dir = "build_$variant";
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my $dir = "build_$variant";
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`rm -rf $dir`;
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mkdir $dir;
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`cp *.vhd* $dir`;
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... | ... | |
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`cp slave_timing_6502$bus.vhd $dir/slave_timing_6502.vhd`;
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`cp swapbits $dir`;
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`cp $type$board.sdc $dir/$type.sdc`;
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`cp $type$board$noflash.sdc $dir/$type.sdc`;
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`cp $type*.qpf $dir`;
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`cp -r int_osc* $dir`;
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`cp -r pll* $dir`;
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atari_chips/pokeyv2/pokeymax.sdc | ||
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-group { CLK_SLOW } \
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-group { \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc } \
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-group { \
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pll_inst|altpll_component|auto_generated|pll1|clk[0] \
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pll_inst|altpll_component|auto_generated|pll1|clk[1] \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
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} \
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-group { \
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pll_inst|altpll_component|auto_generated|pll1|clk[2] \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
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}
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# IOX_RST : OUT STD_LOGIC;
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atari_chips/pokeyv2/pokeymax_noflash.sdc | ||
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create_clock -period 1.9MHz [get_ports PHI2]
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create_clock -period 87.36MHz [get_ports CLK_SLOW]
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derive_pll_clocks
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derive_clock_uncertainty
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set_clock_groups -asynchronous \
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-group { PHI2 } \
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-group { CLK_SLOW } \
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-group { \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
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} \
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-group { \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
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}
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# IOX_RST : OUT STD_LOGIC;
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# IOX_INT : IN STD_LOGIC;
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# IOX_SDA : INOUT STD_LOGIC;
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# IOX_SCL : INOUT STD_LOGIC
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#create_clock -period 56.67MHz -name cart_clk
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#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
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#
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atari_chips/pokeyv2/pokeymaxv1_noflash.sdc | ||
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create_clock -period 1.9MHz [get_ports PHI2]
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create_clock -period 87.36MHz [get_ports CLK_SLOW]
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derive_pll_clocks
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derive_clock_uncertainty
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set_clock_groups -asynchronous \
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-group { PHI2 } \
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-group { CLK_SLOW } \
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-group { \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
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} \
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-group { \
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\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
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}
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# IOX_RST : OUT STD_LOGIC;
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# IOX_INT : IN STD_LOGIC;
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# IOX_SDA : INOUT STD_LOGIC;
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# IOX_SCL : INOUT STD_LOGIC
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#create_clock -period 56.67MHz -name cart_clk
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#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
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#
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#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
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#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
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#
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#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
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#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
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#
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Also available in: Unified diff
Reviewed remaining sdc files