Revision 1333
Added by markw almost 4 years ago
atari_chips/pokeyv2/flash_controller.vhd | ||
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signal flash_data_burstcount : std_logic_vector(1 downto 0);
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signal state_reg : std_logic_vector(2 downto 0);
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signal state_next : std_logic_vector(2 downto 0);
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constant state_idle : std_logic_vector(2 downto 0) := "000";
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constant state_read : std_logic_vector(2 downto 0) := "001";
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constant state_write : std_logic_vector(2 downto 0) := "010";
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constant state_read_wait : std_logic_vector(2 downto 0) := "011";
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constant state_delay : std_logic_vector(2 downto 0) := "100";
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constant state_delay2 : std_logic_vector(2 downto 0) := "101";
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constant state_delay3 : std_logic_vector(2 downto 0) := "110";
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constant state_delay4 : std_logic_vector(2 downto 0) := "111";
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signal state_reg : std_logic_vector(3 downto 0);
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signal state_next : std_logic_vector(3 downto 0);
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constant state_idle : std_logic_vector(3 downto 0) := "0000";
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constant state_read : std_logic_vector(3 downto 0) := "0001";
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constant state_write : std_logic_vector(3 downto 0) := "0010";
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constant state_read_wait : std_logic_vector(3 downto 0) := "0011";
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constant state_delay : std_logic_vector(3 downto 0) := "0100";
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constant state_delay2 : std_logic_vector(3 downto 0) := "0101";
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constant state_delay3 : std_logic_vector(3 downto 0) := "0110";
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constant state_delay4 : std_logic_vector(3 downto 0) := "0111";
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constant state_write_wait : std_logic_vector(3 downto 0) := "1000";
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signal request_addr_reg : std_logic_vector(addr_bits-1 downto 0);
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signal request_addr_next : std_logic_vector(addr_bits-1 downto 0);
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... | ... | |
signal update_robin : std_logic;
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signal flash_read : std_logic;
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signal flash_readvalid : std_logic;
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signal flash_write : std_logic;
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signal flash_write_next : std_logic;
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signal flash_write_reg : std_logic;
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signal flash_waitrequest : std_logic;
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signal flash_do : std_logic_vector(31 downto 0);
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... | ... | |
robin_reg <= "10000000";
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flash_do_reg <= (others=>'0');
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flash_complete_reg <= (others=>'0');
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flash_write_reg <= '0';
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elsif (clk'event and clk='1') then
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state_reg <= state_next;
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request_addr_reg <= request_addr_next;
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... | ... | |
robin_reg <= robin_next;
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flash_do_reg <= flash_do_next;
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flash_complete_reg <= flash_complete_next;
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flash_write_reg <= flash_write_next;
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end if;
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end process;
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... | ... | |
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flash_readvalid, flash_waitrequest,
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flash_write_reg,
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complete,
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update_robin
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)
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... | ... | |
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complete <= '0';
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flash_read <= '0';
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flash_write <= '0';
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flash_write_next <= flash_write_reg;
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device := '0';
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addr := (others=>'0');
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... | ... | |
flash_read <= '1';
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state_next <= state_read_wait;
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when state_read_wait =>
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flash_read <= flash_waitrequest;
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complete <= flash_readvalid;
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if (flash_readvalid = '1') then
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complete <= '1';
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state_next <= state_delay;
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end if;
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when state_write=>
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flash_write <= '1';
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complete <= not(flash_waitrequest);
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flash_write_next <= '1';
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state_next <= state_write_wait;
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when state_write_wait=>
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if (flash_waitrequest='0') then
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flash_write_next <= '0';
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complete <= '1';
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state_next <= state_delay;
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end if;
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when state_delay=>
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... | ... | |
when state_delay3=>
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state_next <= state_delay4;
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when state_delay4=>
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state_next <= state_idle;
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if (flash_waitrequest='0') then
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state_next <= state_idle;
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end if;
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when others=>
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state_next <= state_idle;
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end case;
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... | ... | |
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-- mux on selected device
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process(device_reg, flash_data_do, flash_config_do,
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flash_write,flash_read,flash_data_readvalid,flash_data_waitrequest)
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flash_write_reg,flash_read,flash_data_readvalid,flash_data_waitrequest)
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begin
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flash_do <= (others=>'0');
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... | ... | |
if (device_reg='1') then --config
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flash_do <= flash_config_do;
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flash_config_read <= flash_read;
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flash_config_write <= flash_write;
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flash_config_write <= flash_write_reg;
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flash_readvalid <= '1';
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elsif (device_reg='0') then --main
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flash_do <= flash_data_do;
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flash_data_read <= flash_read;
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flash_data_write <= flash_write;
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flash_data_write <= flash_write_reg;
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flash_readvalid <= flash_data_readvalid;
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flash_waitrequest <= flash_data_waitrequest;
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end if;
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Also available in: Unified diff
Tighten up some timings.