EclaireXL

POT_RESET : IN STD_LOGIC;

KEYBOARD_SCAN : IN STD_LOGIC_VECTOR(5 downto 0);

KEYBOARD_RESPONSE : OUT STD_LOGIC_VECTOR(1 downto 0);

KEYBOARD_SCAN_ENABLE : OUT STD_LOGIC

);

END iox_glue;

ACLK : OUT STD_LOGIC;

BCLK : INOUT STD_LOGIC;

SID : IN STD_LOGIC;

CS1 : IN STD_LOGIC;

AUD : OUT STD_LOGIC_VECTOR(4 DOWNTO 1);

EXT : INOUT STD_LOGIC_VECTOR(EXT_BITS DOWNTO 1);

PADDLE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

IOX_RST : OUT STD_LOGIC;

IOX_INT : IN STD_LOGIC;

EXT_INT(0) <= '0'; --force to 0

EXT_INT(17 downto ext_bits+1) <= (others=>'1');

- EXT_INT(18) <= CS0_N;

EXT_INT(19) <= CS1;

EXT_INT(20) <= '1';

EXT_INT(ext_bits downto 1) <= EXT;

int=>iox_int,

+ pot_reset=>potreset,

keyboard_scan=>keyboard_scan,

D <= BUS_DATA when BUS_OE='1' else (others=>'Z');

-POTRESET_N <= not(POTRESET) when ext_clk_enable=0 else '1';

set_global_assignment -name VHDL_FILE audiotypes.vhdl

set_global_assignment -name VHDL_FILE mixer.vhdl

set_global_assignment -name VHDL_FILE clockgen.vhd

set_global_assignment -name VHDL_FILE pokeymax.vhd

set_global_assignment -name VHDL_FILE PSG/envelope.vhdl

set_global_assignment -name VHDL_FILE PSG/noise.vhdl

fancy_switch_bit : integer := 20; -- 0=ext is low => mono

gtia_audio_bit : integer := 0; -- 0=no gtia on l/r,1=gtia mixed on l/r

detect_right_on_by_default : integer := 1;

a4_bit : integer := 0;

a5_bit : integer := 0;

a6_bit : integer := 0;

a7_bit : integer := 0;

cs0_bit : integer := 18;

cs1_bit : integer := 19;

ext_bits : integer := 3;

enable_config : integer := 1;

enable_sid : integer := 0;

enable_sample : integer := 0;

enable_flash : integer := 0;

enable_audout2: integer := 1;

sid_wave_base : integer := 42496; --to_integer(unsigned(x"a600"));

CLK_OUT : OUT STD_LOGIC; -- Use PHI2 and internal oscillator to create a clock, feed out here

CLK_SLOW : IN STD_LOGIC; -- ... and back in here, then to pll!

D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);

A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

);

end component;

signal OSC_CLK : std_logic; -- about 82MHz! Always?? Massive range on data sheet

signal CLK : std_logic;

SIGNAL POKEY_WRITE_ENABLE : STD_LOGIC_VECTOR(3 downto 0);

SIGNAL SID_WRITE_ENABLE : STD_LOGIC_VECTOR(1 downto 0);

SIGNAL PSG_WRITE_ENABLE : STD_LOGIC_VECTOR(1 downto 0);

signal SIO_TXD : std_logic;

signal SIO_RXD : std_logic;

signal POKEY_IRQ : std_logic_vector(3 downto 0);

signal AUDIO_3_SIGMADELTA : std_logic;

signal KEYBOARD_SCAN : std_logic_vector(5 downto 0);

signal KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);

signal KEYBOARD_SCAN_UPDATE : std_logic;

signal KEYBOARD_SCAN_ENABLE : std_logic;

signal MHZ1_ENABLE : std_logic;

signal MHZ2_ENABLE : std_logic;

function getByte(a : string; x : integer) return std_logic_vector is

variable ret : std_logic_vector(7 downto 0);

begin

CLK_OUT <= OSC_CLK;

pll_inst : pll

PORT MAP(inclk0 => CLK_SLOW,

c0 => CLK, --56 ish

c1 => CLK116, --113ish

c2 => CLK106, --106ish

locked => RESET_N);

AIN(3 downto 0) <= A;

AIN(7) <= EXT_INT(a7_bit);

AIN(6) <= EXT_INT(a6_bit);

ENABLE => SID_CLK_ENABLE, --1MHz

WRITE_ENABLE => SID_WRITE_ENABLE(0),

ADDR => ADDR_IN(4 downto 0),

DI => WRITE_DATA(7 downto 0),

DO => SID_DO(0),

--EXTFILTER_EN => '0',

AUDIO => SID_AUDIO(0),

rom_addr => sid_flash1_addr,

rom_data => flash_do_slow,

rom_request => sid_flash1_romrequest,

ENABLE => SID_CLK_ENABLE, --1MHz

WRITE_ENABLE => SID_WRITE_ENABLE(1),

ADDR => ADDR_IN(4 downto 0),

DI => WRITE_DATA(7 downto 0),

DO => SID_DO(1),

--EXTFILTER_EN => '0',

AUDIO => SID_AUDIO(1),

rom_addr => sid_flash2_addr,

rom_data => flash_do_slow,

rom_request => sid_flash2_romrequest,

RESTRICT_CAPABILITY_REG

)

variable writereq : std_logic;

variable enable_region : std_logic;

begin

writereq := not(write_n) and request;

POKEY_WRITE_ENABLE <= (others=>'0');

SID_WRITE_ENABLE <= (others=>'0');

PSG_WRITE_ENABLE <= (others=>'0');

SAMPLE_WRITE_ENABLE <= '0';

CONFIG_WRITE_ENABLE <= '0';

DO_MUX <= SID_DO(0);

DRIVE_DO_MUX <= SID_DRIVE_DO(0);

SID_WRITE_ENABLE(0) <= writereq;

when "0110"|"0111" =>

enable_region := RESTRICT_CAPABILITY_REG(2);

DO_MUX <= SID_DO(1);

DRIVE_DO_MUX <= SID_DRIVE_DO(1);

SID_WRITE_ENABLE(1) <= writereq;

when "1000"|"1001" =>

enable_region := RESTRICT_CAPABILITY_REG(4);

DO_MUX <= SAMPLE_DO;

end if;

IRQ_EN_REG <= '0';

CHANNEL_MODE_REG <= '0';

POST_DIVIDE_REG <= "10100000"; -- 1/2 5v, 3/4 1v

GTIA_ENABLE_REG <= "1100"; -- external only

CONFIG_ENABLE_REG <= '0';

CHANNEL_MODE_NEXT <= flash_do_slow(2);

IRQ_EN_NEXT <= flash_do_slow(3);

DETECT_RIGHT_NEXT <= flash_do_slow(4);

POST_DIVIDE_NEXT <= flash_do_slow(15 downto 8);

GTIA_ENABLE_NEXT <= flash_do_slow(19 downto 16);

-- 23 downto 20 reserved

-- 6-7 reserved

RESTRICT_CAPABILITY_NEXT <= flash_do_slow(12 downto 8);

-- 13-15 reserved

when others =>

end case;

elsif (CONFIG_WRITE_ENABLE='1') then

CH7 => unsigned(SID_AUDIO(1)),

CH8 => unsigned(PSG_AUDIO(0)),

CH9 => unsigned(PSG_AUDIO(1)),

CHA(15) => GTIA_AUDIO,

AUDIO_0_UNSIGNED => AUDIO_0_UNSIGNED,

AUDOUT => AUDIO_3_SIGMADELTA

);

-- io extension

-- drive to 0 for pot reset (otherwise high imp)

-- drive keyboard lines

pot_reset=>potreset,

keyboard_scan=>keyboard_scan,

keyboard_scan_enable=>keyboard_scan_enable

);

-- Wire up pins

ACLK <= SIO_CLOCKOUT;

BCLK <= '0' when (SIO_CLOCKIN_OE='1' and SIO_CLOCKIN_OUT='0') else 'Z';

SOD <= '0' when SIO_TXD='0' else 'Z';

SIO_RXD <= SID;

--1->pin37