Project

General

Profile

« Previous | Next » 

Revision 1314

Added by markw over 4 years ago

Reset ps2 after pll change in case of stuck keys

View differences:

mcc216/atari800core_mcc.vhd
signal csync : std_logic;
signal video_mode : std_logic_vector(2 downto 0);
-- pll switch
signal pll_reconfig_done : std_logic;
BEGIN
USB2_N <= USBWireVPout when USBWireOE_n='0' else 'Z';
......
PLL_CLKS(3) => open,
PLL_CLKS(4) => SCANDOUBLE_CLK,
RESET_N_OUT => RESET_N
RESET_N_OUT => RESET_N,
PLL_RECONFIG_DONE => PLL_RECONFIG_DONE
);
SVIDEO_DAC_CLK <= SCANDOUBLE_CLK;
end generate;
......
PORT MAP
(
CLK => clk,
RESET_N => reset_n,
RESET_N => reset_n and not(PLL_RECONFIG_DONE),
PS2_CLK => ps2k_clk,
PS2_DAT => ps2k_dat,
mcc216/switch_pal_ntsc.vhd
INPUT_CLK : IN STD_LOGIC;
PLL_CLKS : OUT STD_LOGIC_VECTOR(CLOCKS-1 downto 0);
RESET_N_OUT : OUT STD_LOGIC
RESET_N_OUT : OUT STD_LOGIC;
PLL_RECONFIG_DONE : OUT STD_LOGIC
);
END switch_pal_ntsc;
......
signal reconfig_to_pal_reg : std_logic;
signal reconfig_to_pal_next : std_logic;
signal pll_enable_reg_sync_reg : std_logic;
BEGIN
......
pll_enable_synchronizer : entity work.synchronizer
port map (clk=>CLK_RAW(SYNC_ON), raw=>pll_enable_reg, sync=>pll_enable_reg_sync);
pll_reconfig_done <= '1' when pll_enable_reg_sync_reg='0' and pll_enable_reg_sync='1' else '0';
process(CLK_RAW)
begin
if (CLK_RAW(SYNC_ON)'event and CLK_RAW(SYNC_ON)='1') then
pll_enable_reg_sync_reg <= pll_enable_reg_sync;
end if;
end process;
GEN_CLKCTRL:
for I in 0 to (CLOCKS-1) generate

Also available in: Unified diff