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-- ZX Spectrum for Altera DE1
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--
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-- Copyright (c) 2009-2010 Mike Stirling
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-- Modified by Mark Watson for the Atari800
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- * Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- * Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity i2s_intf is
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generic(
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inclk_rate : positive := 25000000;
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sample_rate : positive := 8000;
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preamble : positive := 1; -- I2S
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word_length : positive := 16
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);
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port (
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CLK : in std_logic;
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nRESET : in std_logic;
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-- Parallel IO
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PCM_INL : out std_logic_vector(word_length - 1 downto 0);
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PCM_INR : out std_logic_vector(word_length - 1 downto 0);
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PCM_OUTL : in std_logic_vector(word_length - 1 downto 0);
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PCM_OUTR : in std_logic_vector(word_length - 1 downto 0);
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-- Codec interface (right justified mode)
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-- LRCLK is equal to the sample rate and is synchronous to
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-- MCLK. It must be related to MCLK by the oversampling ratio
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-- given in the codec datasheet.
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I2S_LRCLK : out std_logic;
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-- Data is shifted out on the falling edge of BCLK, sampled
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-- on the rising edge. The bit rate is determined such that
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-- it is fast enough to fit preamble + word_length bits into
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-- each LRCLK half cycle. The last cycle of each word may be
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-- stretched to fit to LRCLK. This is OK at least for the
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-- WM8731 codec.
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-- The first falling edge of each timeslot is always synchronised
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-- with the LRCLK edge.
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I2S_BCLK : out std_logic;
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-- Output bitstream
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I2S_DOUT : out std_logic;
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-- Input bitstream
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I2S_DIN : in std_logic
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);
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end i2s_intf;
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architecture i2s_intf_arch of i2s_intf is
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constant ratio_mclk_fs : positive := (inclk_rate / sample_rate);
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constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
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constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
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constant nbits : positive := preamble + word_length;
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subtype lrdivider_t is integer range 0 to lrdivider_top;
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subtype bdivider_t is integer range 0 to bdivider_top;
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subtype bitcount_t is integer range 0 to nbits;
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signal lrdivider : lrdivider_t;
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signal bdivider : bdivider_t;
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signal bitcount : bitcount_t;
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signal lrclk_r : std_logic;
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signal bclk_r : std_logic;
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-- Shift register is long enough for the number of data bits
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-- plus the preamble, plus an extra bit on the right to register
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-- the incoming data
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signal shiftreg : std_logic_vector(nbits downto 0);
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begin
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I2S_LRCLK <= lrclk_r;
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I2S_BCLK <= bclk_r;
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I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
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process(nRESET,CLK)
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begin
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if nRESET = '0' then
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PCM_INL <= (others => '0');
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PCM_INR <= (others => '0');
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-- Preload down-counters for clock generation
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lrdivider <= lrdivider_top;
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bdivider <= bdivider_top;
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bitcount <= nbits;
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lrclk_r <= '0';
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bclk_r <= '0';
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shiftreg <= (others => '0');
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elsif rising_edge(CLK) then
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-- Generate LRCLK at rate specified by codec configuration
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if lrdivider = 0 then
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-- LRCLK divider has reached 0 - start again from the top
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lrdivider <= lrdivider_top;
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-- Generate LRCLK edge and sync the BCLK counter
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lrclk_r <= not lrclk_r;
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bclk_r <= '0';
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bitcount <= nbits; -- 1 extra required for setup
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bdivider <= bdivider_top;
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-- Load shift register with output data padding preamble
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-- with 0s. Load output buses with input word from the
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-- previous timeslot.
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shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
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if lrclk_r = '0' then
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-- Previous channel input is LEFT. This is available in the
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-- shift register at the end of a cycle, right justified
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PCM_INL <= shiftreg(word_length - 1 downto 0);
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-- Next channel to output is RIGHT. Load this into the
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-- shift register at the start of a cycle, left justified
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shiftreg(word_length downto 1) <= PCM_OUTR;
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else
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-- Previous channel input is RIGHT
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PCM_INR <= shiftreg(word_length - 1 downto 0);
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-- Next channel is LEFT
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shiftreg(word_length downto 1) <= PCM_OUTL;
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end if;
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else
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-- Decrement the LRCLK counter
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lrdivider <= lrdivider - 1;
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-- Generate BCLK at a suitable rate to fit the required number
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-- of bits into each timeslot. Data is changed on the falling edge,
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-- sampled on the rising edge
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if bdivider = 0 then
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-- If all bits have been output for this phase then
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-- stop and wait to sync back up with LRCLK
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if bitcount > 0 then
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-- Reset
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bdivider <= bdivider_top;
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-- Toggle BCLK
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bclk_r <= not bclk_r;
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if bclk_r = '0' then
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-- Rising edge - shift in current bit and decrement bit counter
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bitcount <= bitcount - 1;
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shiftreg(0) <= I2S_DIN;
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else
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-- Falling edge - shift out next bit
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shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
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end if;
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end if;
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else
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-- Decrement the BCLK counter
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bdivider <= bdivider - 1;
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end if;
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end if;
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end if;
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end process;
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end i2s_intf_arch;
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