repo2/common/components/scandoubler.vhdl @ 111
| 1 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY scandoubler IS
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| 80 | markw | GENERIC
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(
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video_bits : integer := 4
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);
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| 1 | markw | PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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VGA : IN STD_LOGIC;
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COMPOSITE_ON_HSYNC : in std_logic;
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colour_enable : in std_logic;
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doubled_enable : in std_logic;
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-- GTIA interface
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colour_in : in std_logic_vector(7 downto 0);
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vsync_in : in std_logic;
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hsync_in : in std_logic;
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-- TO TV...
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| 80 | markw | R : OUT STD_LOGIC_vector(video_bits-1 downto 0);
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G : OUT STD_LOGIC_vector(video_bits-1 downto 0);
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B : OUT STD_LOGIC_vector(video_bits-1 downto 0);
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| 1 | markw | ||
VSYNC : out std_logic;
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HSYNC : out std_logic
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);
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END scandoubler;
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ARCHITECTURE vhdl OF scandoubler IS
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COMPONENT gtia_palette IS
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PORT
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(
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ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
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R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
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G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
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B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
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);
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END component;
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-- component reg_file IS
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-- generic
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-- (
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-- BYTES : natural := 1;
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-- WIDTH : natural := 1
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-- );
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-- PORT
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-- (
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-- CLK : IN STD_LOGIC;
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-- ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
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-- DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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-- WR_EN : IN STD_LOGIC;
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--
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-- DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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-- );
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-- END component;
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component scandouble_ram_infer IS
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PORT
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(
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clock: IN std_logic;
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data: IN std_logic_vector (7 DOWNTO 0);
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address: IN integer RANGE 0 to 1824;
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we: IN std_logic;
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q: OUT std_logic_vector (7 DOWNTO 0)
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);
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END component;
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component delay_line IS
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generic(COUNT : natural := 1);
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PORT
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(
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CLK : IN STD_LOGIC;
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SYNC_RESET : IN STD_LOGIC;
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DATA_IN : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
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RESET_N : IN STD_LOGIC;
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DATA_OUT : OUT STD_LOGIC
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);
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END component;
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signal colour_next : std_logic_vector(7 downto 0);
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signal colour_reg : std_logic_vector(7 downto 0);
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signal vsync_next : std_logic;
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signal vsync_reg : std_logic;
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signal hsync_next : std_logic;
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signal hsync_reg : std_logic;
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signal r_next : std_logic_vector(7 downto 0);
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signal g_next : std_logic_vector(7 downto 0);
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signal b_next : std_logic_vector(7 downto 0);
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signal r_reg : std_logic_vector(7 downto 0);
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signal g_reg : std_logic_vector(7 downto 0);
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signal b_reg : std_logic_vector(7 downto 0);
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signal linea_address : std_logic_vector(10 downto 0);
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signal linea_write_enable : std_logic;
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signal linea_out : std_logic_vector(7 downto 0);
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signal lineb_address : std_logic_vector(10 downto 0);
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signal lineb_write_enable : std_logic;
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signal lineb_out : std_logic_vector(7 downto 0);
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signal input_address_next : std_logic_vector(10 downto 0);
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signal input_address_reg : std_logic_vector(10 downto 0);
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signal output_address_next : std_logic_vector(10 downto 0);
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signal output_address_reg : std_logic_vector(10 downto 0);
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signal buffer_select_next : std_logic;
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signal buffer_select_reg : std_logic;
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signal hsync_in_reg : std_logic;
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signal vga_hsync_next : std_logic;
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signal vga_hsync_reg : std_logic;
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signal vga_hsync_start : std_logic;
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signal vga_hsync_end : std_logic;
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begin
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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r_reg <= (others=>'0');
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g_reg <= (others=>'0');
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b_reg <= (others=>'0');
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colour_reg <= (others=>'0');
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hsync_reg <= '0';
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vsync_reg <= '0';
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input_address_reg <= (others=>'0');
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output_address_reg <= (others=>'0');
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buffer_select_reg <= '0';
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vga_hsync_reg <= '0';
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elsif (clk'event and clk='1') then
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r_reg <= r_next;
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g_reg <= g_next;
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b_reg <= b_next;
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colour_reg <= colour_next;
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hsync_reg <= hsync_next;
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vsync_reg <= vsync_next;
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input_address_reg <= input_address_next;
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output_address_reg <= output_address_next;
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buffer_select_reg <= buffer_select_next;
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hsync_in_reg <= hsync_in;
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vga_hsync_reg <= vga_hsync_next;
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end if;
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end process;
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-- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!!
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-- linea : reg_file
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--generic map (BYTES=>456,WIDTH=>9)
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--port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out);
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--lineb : reg_file
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-- generic map (BYTES=>456,WIDTH=>9)
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-- port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);
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linea : scandouble_ram_infer
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port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
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lineb : scandouble_ram_infer
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port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);
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-- capture
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process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
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begin
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input_address_next <= input_address_reg;
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buffer_select_next <= buffer_select_reg;
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linea_write_enable <= '0';
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lineb_write_enable <= '0';
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if (colour_enable = '1') then
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input_address_next <= std_logic_vector(unsigned(input_address_reg)+1);
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linea_write_enable <= buffer_select_reg;
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lineb_write_enable <= not(buffer_select_reg);
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end if;
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if (hsync_in = '1' and hsync_in_reg = '0') then
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input_address_next <= (others=>'0');
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buffer_select_next <= not(buffer_select_reg);
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end if;
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end process;
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-- output
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process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable)
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begin
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output_address_next <= output_address_reg;
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vga_hsync_start<='0';
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vga_hsync_next <= vga_hsync_reg;
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if (doubled_enable = '1') then
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output_address_next <= std_logic_vector(unsigned(output_address_reg)+1);
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if (output_address_reg = "111"&X"1F") then
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output_address_next <= (others=>'0');
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vga_hsync_start <= '1';
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vga_hsync_next <= '1';
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end if;
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end if;
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if (vga_hsync_end = '1') then
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vga_hsync_next <= '0';
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end if;
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end process;
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linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg;
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lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg;
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hsync_delay : delay_line
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generic map (COUNT=>128)
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port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end);
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-- display
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process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out)
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begin
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colour_next <= colour_reg;
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vsync_next <= vsync_reg;
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hsync_next <= hsync_reg;
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if (vga = '0') then
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-- non-vga mode - pass through
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colour_next <= colour_in;
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vsync_next <= not(vsync_in);
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--hsync_next <= not(hsync_in or vsync_in);
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if (composite_on_hsync = '1') then
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hsync_next <= not(hsync_in xor vsync_in);
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else
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hsync_next <= not(hsync_in);
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end if;
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else
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-- vga mode, store all inputs - then play back!
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if (buffer_select_reg = '0') then
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colour_next <= linea_out; -- todo, smoothly increase/decrease...
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else
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colour_next <= lineb_out;
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end if;
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vsync_next <= not(vsync_in);
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--hsync_next <= not(vga_hsync_reg);
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if (composite_on_hsync = '1') then
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hsync_next <= not(vga_hsync_reg xor vsync_in);
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else
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hsync_next <= not(vga_hsync_reg);
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end if;
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end if;
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end process;
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-- colour palette
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-- Color Value Color Value
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--Black 0, 0 Medium blue 8, 128
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--Rust 1, 16 Dark blue 9, 144
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--Red-orange 2, 32 Blue-grey 10, 160
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--Dark orange 3, 48 Olive green 11, 176
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--Red 4, 64 Medium green 12, 192
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--Dk lavender 5, 80 Dark green 13, 208
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--Cobalt blue 6, 96 Orange-green 14, 224
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--Ultramarine 7, 112 Orange 15, 240
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-- from altirra
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palette1 : entity work.gtia_palette(altirra)
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port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next);
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-- from lao
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-- palette2 : entity work.gtia_palette(laoo)
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-- port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);
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-- output
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-- TODO - for DE2, output full 8 bits
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| 80 | markw | R <= R_reg(7 downto 8-video_bits);
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G <= G_reg(7 downto 8-video_bits);
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B <= B_reg(7 downto 8-video_bits);
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| 1 | markw | ||
vsync<=vsync_reg;
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hsync<=hsync_reg;
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end vhdl;
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