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Revision 1101

Added by markw over 5 years ago

Make acid test pass again, while still having fujinet work

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common/a8core/atari800core.vhd
EN => PIA_READ_ENABLE,
WR_EN => PIA_WRITE_ENABLE,
RESET_N => RESET_N,
ENABLE_ORIG => ENABLE_179_MEMWAIT,
CA1 => CA1_IN,
CB1 => CB1_IN,
CA2_DIR_OUT => CA2_DIR_OUT,
common/a8core/pia.vhdl
EN : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
ENABLE_ORIG : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
CA1 : IN STD_LOGIC;
......
end if;
if (addr_decoded(2) = '1') then
data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
data_out <= (irqa_reg(1)&irqa_reg(0) and not(porta_control_reg(5))&not(porta_control_reg(5)))&porta_control_reg;
end if;
if (addr_decoded(3) = '1') then
data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
data_out <= (irqb_reg(1)&irqb_reg(0) and not(portb_control_reg(5))&not(portb_control_reg(5)))&portb_control_reg;
end if;
end if;
......
-- irq handing
-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
process (irqa_next, irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1_SYNC, CA1_reg, ca2_in_SYNC, ca2_reg, ca1_edge_reg, ca2_edge_reg)
process (irqa_next, irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1_SYNC, CA1_reg, ca2_in_SYNC, ca2_reg, ca1_edge_reg, ca2_edge_reg, ENABLE_ORIG)
begin
irqa_next(1) <= irqa_reg(1) and not(read_ora);
irqa_next(0) <= irqa_reg(0) and not(read_ora);
......
end if;
if (CA2_in_SYNC = '1' and CA2_reg = '0') then
irqa_next(0) <= ca2_edge_reg or irqa_next(0);
irqa_next(0) <= ca2_edge_reg or (irqa_next(0) and not(porta_control_reg(5)));
end if;
if (CA2_in_SYNC = '0' and CA2_reg = '1') then
irqa_next(0) <= not(ca2_edge_reg) or irqa_next(0);
end if;
if (CA2_in_SYNC = '0' and CA2_reg = '1') then
irqa_next(0) <= not(ca2_edge_reg) or (irqa_next(0) and not(porta_control_reg(5)));
end if;
ca1_edge_next <= porta_control_next(1); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
......
if (porta_control_next(5) = '0') then -- CA2 is an input
else -- CA2 is an output
--irqa_next(0) <= '0';
case porta_control_next(4 downto 3) is
when "10" =>
ca2_output_next <= '0'; -- direct control
......
when "01" =>
if (read_ora = '1') then
ca2_output_next <= '0';
else
elsif (ENABLE_ORIG='1') then
-- clock restore
ca2_output_next <= '1';
end if;
......
end process;
process (irqb_next, irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1_SYNC, CB1_reg, cb2_in_SYNC, cb2_reg, cb1_edge_reg, cb2_edge_reg)
process (irqb_next, irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1_SYNC, CB1_reg, cb2_in_SYNC, cb2_reg, cb1_edge_reg, cb2_edge_reg,enable_orig)
begin
irqb_next(1) <= irqb_reg(1) and not(read_orb);
irqb_next(0) <= irqb_reg(0) and not(read_orb);
......
end if;
if (CB1_SYNC = '0' and CB1_reg = '1') then
irqb_next(1) <= not(cb1_edge_reg) or irqb_next(1);
end if;
end if;
if (CB2_in_SYNC = '1' and CB2_reg = '0') then
irqb_next(0) <= cb2_edge_reg or irqb_next(0);
irqb_next(0) <= cb2_edge_reg or (irqb_next(0) and not(portb_control_reg(5)));
end if;
if (CB2_in_SYNC = '0' and CB2_reg = '1') then
irqb_next(0) <= not(cb2_edge_reg) or irqb_next(0);
end if;
irqb_next(0) <= not(cb2_edge_reg) or (irqb_next(0) and not(portb_control_reg(5)));
end if;
cb1_edge_next <= portb_control_next(1); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
......
when "01" =>
if (write_orb = '1') then
cb2_output_next <= '0';
else
elsif (ENABLE_ORIG='1') then
-- clock restore
cb2_output_next <= '1';
end if;

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