Revision 1094
Added by markw over 5 years ago
| common/a8core/pia.vhdl | ||
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irqa_next(0) <= not(ca2_edge_reg);
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end if;
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ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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ca1_edge_next <= porta_control_next(1); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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if (porta_control_next(5) = '0') then -- CA2 is an input
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| ... | ... | |
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irqb_next(0) <= not(cb2_edge_reg);
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end if;
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cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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cb1_edge_next <= portb_control_next(1); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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if (portb_control_next(5) = '0') then -- CB2 is an input
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| ... | ... | |
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portb_dir_out <= portb_direction_reg;
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portb_input_next <= portb_in;
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irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
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irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
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irqa_n <= not((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3) and not(porta_control_reg(5))));
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irqb_n <= not((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3) and not(portb_control_reg(5))));
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end vhdl;
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Correct edge bit. Also interrupt 1 should still work in output mode.