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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY pia IS
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PORT
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(
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CLK : IN STD_LOGIC;
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ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
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CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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EN : IN STD_LOGIC;
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WR_EN : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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CA1 : IN STD_LOGIC;
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CB1 : IN STD_LOGIC;
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CA2_DIR_OUT : OUT std_logic;
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CA2_OUT : OUT std_logic;
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CA2_IN : IN STD_LOGIC;
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CB2_DIR_OUT : OUT std_logic;
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CB2_OUT : OUT std_logic;
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CB2_IN : IN STD_LOGIC;
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-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
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PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- pull up - i.e. 0 driven only
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PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
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PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
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PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
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PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
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PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
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-- CPU interface
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DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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IRQA_N : OUT STD_LOGIC;
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IRQB_N : OUT STD_LOGIC
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);
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END pia;
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ARCHITECTURE vhdl OF pia IS
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COMPONENT complete_address_decoder IS
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generic (width : natural := 1);
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PORT
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(
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addr_in : in std_logic_vector(width-1 downto 0);
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addr_decoded : out std_logic_vector((2**width)-1 downto 0)
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);
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END component;
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signal addr_decoded : std_logic_vector(3 downto 0);
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signal porta_output_next : std_logic_vector(7 downto 0);
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signal porta_output_reg : std_logic_vector(7 downto 0);
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signal porta_input_reg : std_logic_vector(7 downto 0);
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signal porta_input_next : std_logic_vector(7 downto 0);
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signal porta_direction_next : std_logic_vector(7 downto 0);
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signal porta_direction_reg : std_logic_vector(7 downto 0);
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signal porta_control_next : std_logic_vector(5 downto 0);
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signal porta_control_reg : std_logic_vector(5 downto 0);
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signal portb_output_next : std_logic_vector(7 downto 0);
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signal portb_output_reg : std_logic_vector(7 downto 0);
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signal portb_input_reg : std_logic_vector(7 downto 0);
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signal portb_input_next : std_logic_vector(7 downto 0);
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signal portb_direction_next : std_logic_vector(7 downto 0);
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signal portb_direction_reg : std_logic_vector(7 downto 0);
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signal portb_control_next : std_logic_vector(5 downto 0);
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signal portb_control_reg : std_logic_vector(5 downto 0);
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signal irqa_next : std_logic_vector(1 downto 0);
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signal irqa_reg : std_logic_vector(1 downto 0);
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signal irqb_next : std_logic_vector(1 downto 0);
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signal irqb_reg : std_logic_vector(1 downto 0);
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signal CA1_reg : std_logic;
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signal CA2_reg : std_logic;
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signal CB1_reg : std_logic;
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signal CB2_reg : std_logic;
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signal CA2_output_next : std_logic;
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signal CA2_output_reg : std_logic;
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signal CB2_output_next : std_logic;
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signal CB2_output_reg : std_logic;
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signal read_ora : std_logic;
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signal read_orb : std_logic;
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signal write_ora : std_logic;
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signal write_orb : std_logic;
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signal ca1_edge_next : std_logic;
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signal ca1_edge_reg : std_logic;
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signal ca2_edge_next : std_logic;
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signal ca2_edge_reg : std_logic;
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signal cb1_edge_next : std_logic;
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signal cb1_edge_reg : std_logic;
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signal cb2_edge_next : std_logic;
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signal cb2_edge_reg : std_logic;
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begin
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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porta_output_reg <= (others=>'0');
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porta_input_reg <= (others=>'0');
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porta_direction_reg <= (others=>'0'); -- default to input
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porta_control_reg <= (others=>'0');
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portb_output_reg <= X"FF"; -- all high to ensure we have OS Rom enabled
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portb_input_reg <= (others=>'0');
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portb_direction_reg <= (others=>'1'); -- default to ouput
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portb_control_reg <= (others=>'0');
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irqa_reg <= (others=>'0');
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irqb_reg <= (others=>'0');
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CA1_reg <= '0';
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CA2_reg <= '0';
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CB1_reg <= '0';
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CB2_reg <= '0';
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CA2_output_reg <= '0';
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CB2_output_reg <= '0';
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ca1_edge_reg <= '0';
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ca2_edge_reg <= '0';
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cb1_edge_reg <= '0';
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cb2_edge_reg <= '0';
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elsif (clk'event and clk='1') then
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porta_output_reg <= porta_output_next;
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porta_input_reg <= porta_input_next;
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porta_direction_reg <= porta_direction_next;
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porta_control_reg <= porta_control_next;
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portb_output_reg <= portb_output_next;
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portb_input_reg <= PORTB_input_next;
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portb_direction_reg <= portb_direction_next;
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portb_control_reg <= portb_control_next;
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irqa_reg <= irqa_next;
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irqb_reg <= irqb_next;
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CA1_reg <= CA1;
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CA2_reg <= CA2_in;
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CB1_reg <= CB1;
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CB2_reg <= CB2_in;
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CA2_output_reg <= CA2_output_next;
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CB2_output_reg <= CB2_output_next;
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ca1_edge_reg <= ca1_edge_next;
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ca2_edge_reg <= ca2_edge_next;
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cb1_edge_reg <= cb1_edge_next;
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cb2_edge_reg <= cb2_edge_next;
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end if;
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end process;
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-- decode address
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decode_addr1 : complete_address_decoder
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generic map(width=>2)
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port map (addr_in=>addr, addr_decoded=>addr_decoded);
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-- Writes to registers
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process(cpu_data_in,wr_en,addr_decoded, porta_output_reg, portb_output_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg)
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begin
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porta_output_next <= porta_output_reg;
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portb_output_next <= portb_output_reg;
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porta_direction_next <= porta_direction_reg;
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portb_direction_next <= portb_direction_reg;
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porta_control_next(5 downto 0) <= porta_control_reg(5 downto 0);
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portb_control_next(5 downto 0) <= portb_control_reg(5 downto 0);
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write_ora <= '0';
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write_orb <= '0';
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if (wr_en = '1') then
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if(addr_decoded(0) = '1') then
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if (porta_control_reg(2) = '1') then
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porta_output_next <= cpu_data_in;
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write_ora <= '1';
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else
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porta_direction_next <= cpu_data_in;
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end if;
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end if;
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if(addr_decoded(1) = '1') then
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if (portb_control_reg(2) = '1') then
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portb_output_next <= cpu_data_in;
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write_orb <= '1';
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else
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portb_direction_next <= cpu_data_in;
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end if;
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end if;
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if(addr_decoded(2) = '1') then
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porta_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
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end if;
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if(addr_decoded(3) = '1') then
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portb_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
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end if;
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end if;
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end process;
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-- Read from registers
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process(addr_decoded, en, porta_input_reg, portb_input_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg, irqa_reg, irqb_reg)
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begin
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data_out <= X"FF";
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read_ora <= '0';
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read_orb <= '0';
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if (EN = '1') then -- since reads have an effect here...
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if (addr_decoded(0) = '1') then
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if (porta_control_reg(2) = '1') then
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data_out <= porta_input_reg;
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read_ora <= '1';
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else
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data_out <= porta_direction_reg; -- can this be read?
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end if;
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end if;
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if (addr_decoded(1) = '1') then
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if (portb_control_reg(2) = '1') then
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data_out <= portb_input_reg;
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read_orb <= '1';
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else
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data_out <= portb_direction_reg; -- can this be read?
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end if;
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end if;
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if (addr_decoded(2) = '1') then
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data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
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end if;
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if (addr_decoded(3) = '1') then
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data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
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end if;
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end if;
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end process;
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-- irq handing
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-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
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process (irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1, CA1_reg, ca2_in, ca2_reg, ca1_edge_reg, ca2_edge_reg)
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begin
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irqa_next(1) <= irqa_reg(1) and not(read_ora);
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irqa_next(0) <= irqa_reg(0) and not(read_ora);
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ca2_output_next <= ca2_output_reg;
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if (CA1 = '1' and CA1_reg = '0') then
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irqa_next(1) <= ca1_edge_reg;
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end if;
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if (CA1 = '0' and CA1_reg = '1') then
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irqa_next(1) <= not(ca1_edge_reg);
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end if;
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if (CA2_in = '1' and CA2_reg = '0') then
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irqa_next(0) <= ca2_edge_reg;
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end if;
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if (CA2_in = '0' and CA2_reg = '1') then
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irqa_next(0) <= not(ca2_edge_reg);
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end if;
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ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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if (porta_control_next(5) = '0') then -- CA2 is an input
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else -- CA2 is an output
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--irqa_next(0) <= '0';
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case porta_control_next(4 downto 3) is
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when "10" =>
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ca2_output_next <= '0'; -- direct control
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when "11" =>
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ca2_output_next <= '1'; -- direct control
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when "01" =>
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if (read_ora = '1') then
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ca2_output_next <= '0';
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else
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-- clock restore
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ca2_output_next <= '1';
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end if;
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when "00" =>
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if (read_ora = '1') then
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ca2_output_next <= '0';
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elsif (irqa_reg(1) = '1') then
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-- ca1 restore
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ca2_output_next <= '1';
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end if;
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end case;
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end if;
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end process;
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process (irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1, CB1_reg, cb2_in, cb2_reg, cb1_edge_reg, cb2_edge_reg)
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begin
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irqb_next(1) <= irqb_reg(1) and not(read_orb);
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irqb_next(0) <= irqb_reg(0) and not(read_orb);
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cb2_output_next <= cb2_output_reg;
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if (CB1 = '1' and CB1_reg = '0') then
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irqb_next(1) <= cb1_edge_reg;
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end if;
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if (CB1 = '0' and CB1_reg = '1') then
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irqb_next(1) <= not(cb1_edge_reg);
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end if;
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if (CB2_in = '1' and CB2_reg = '0') then
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irqb_next(0) <= cb2_edge_reg;
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end if;
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if (CB2_in = '0' and CB2_reg = '1') then
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irqb_next(0) <= not(cb2_edge_reg);
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end if;
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cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
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if (portb_control_next(5) = '0') then -- CB2 is an input
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else -- CB2 is an output
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--irqb_next(0) <= '0';
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case portb_control_next(4 downto 3) is
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when "10" =>
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cb2_output_next <= '0'; -- direct control
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when "11" =>
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cb2_output_next <= '1'; -- direct control
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when "01" =>
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if (write_orb = '1') then
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cb2_output_next <= '0';
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else
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-- clock restore
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cb2_output_next <= '1';
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end if;
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when "00" =>
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if (write_orb = '1') then
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cb2_output_next <= '0';
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elsif (irqb_reg(1) = '1') then
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-- cb1 restore
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cb2_output_next <= '1';
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end if;
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end case;
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end if;
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end process;
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-- output
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-- TODO - review if ca2 and cb2 are push pull or pull up...
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--ca2 <= CA2_output_reg when porta_control_reg(5) = '1' else 'Z';
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--cb2 <= CB2_output_reg when portb_control_reg(5) = '1' else 'Z';
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ca2_out <= CA2_output_reg;
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ca2_dir_out <= porta_control_reg(5);
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cb2_out <= CB2_output_reg;
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cb2_dir_out <= portb_control_reg(5);
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porta_out <= porta_output_reg;
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porta_dir_out <= porta_direction_reg;
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porta_input_next <= porta_in;
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--portb_out <= portb_output_reg;
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-- forced to 1 when in input mode - star raiders relies on this
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portb_out(0) <= portb_output_reg(0) when portb_direction_reg(0)='1' else '1';
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portb_out(1) <= portb_output_reg(1) when portb_direction_reg(1)='1' else '1';
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portb_out(2) <= portb_output_reg(2) when portb_direction_reg(2)='1' else '1';
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portb_out(3) <= portb_output_reg(3) when portb_direction_reg(3)='1' else '1';
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portb_out(4) <= portb_output_reg(4) when portb_direction_reg(4)='1' else '1';
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portb_out(5) <= portb_output_reg(5) when portb_direction_reg(5)='1' else '1';
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portb_out(6) <= portb_output_reg(6) when portb_direction_reg(6)='1' else '1';
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portb_out(7) <= portb_output_reg(7) when portb_direction_reg(7)='1' else '1';
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portb_dir_out <= portb_direction_reg;
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portb_input_next <= portb_in;
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irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
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irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
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end vhdl;
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