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-- ======================================================================================
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-- A generic VHDL entity for a typical SRAM with complete timing parameters
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--
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-- Static memory, version 1.3 9. August 1996
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--
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-- ======================================================================================
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--
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-- (C) Andre' Klindworth, Dept. of Computer Science
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-- University of Hamburg
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-- Vogt-Koelln-Str. 30
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-- 22527 Hamburg
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-- klindwor@informatik.uni-hamburg.de
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--
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-- This VHDL code may be freely copied as long as the copyright note isn't removed from
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-- its header. Full affiliation of anybody modifying this file shall be added to the
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-- header prior to further distribution.
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-- The download procedure originates from DLX memory-behaviour.vhdl:
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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--
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--
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-- Features:
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--
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-- o generic memory size, width and timing parameters
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--
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-- o 18 typical SRAM timing parameters supported
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--
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-- o clear-on-power-up and/or download-on-power-up if requested by generic
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--
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-- o RAM dump into or download from an ASCII-file at any time possible
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-- (requested by signal)
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--
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-- o pair of active-low and active-high Chip-Enable signals
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--
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-- o nWE-only memory access control
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--
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-- o many (but not all) timing and access control violations reported by assertions
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--
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--
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--
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-- RAM data file format:
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--
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-- The format of the ASCII-files for RAM download or dump is very simple:
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-- Each line of the file consists of the memory address (given as a decimal number).
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-- and the corresponding RAM data at this address (given as a binary number).
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-- Any text in a line following the width-th digit of the binary number is ignored.
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-- Please notice that address and data have to be seperated by a SINGLE blank,
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-- that the binary number must have as many digits as specified by the generic width,
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-- and that no additional blanks or blank lines are tolerated. Example:
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--
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-- 0 0111011010111101 This text is interpreted as a comment
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-- 1 1011101010110010
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-- 17 0010001001000100
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--
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--
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-- Hints & traps:
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--
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-- If you have problems using this model, please feel free to to send me an e-mail.
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-- Here are some potential problems which have been reported to me:
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--
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-- o There's a potential problem with passing the filenames for RAM download or
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-- dump via port signals of type string. E.g. for Synopsys VSS, the string
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-- assigned to a filename-port should have the same length as its default value.
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-- If you are sure that you need a download or dump only once during a single
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-- simulation run, you may remove the filename-ports from the interface list
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-- and replace the constant string in the corresponding file declarations.
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--
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-- o Some simulators do not implement all of the standard TEXTIO-functions as
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-- specified by the IEEE Std 1076-87 and IEEE Std 1076-93. Check it out.
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-- If any of the (multiple overloaded) writeline, write, readline or
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-- read functions that are used in this model is missing, you have to
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-- write your own version and you should complain at your simulator tool
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-- vendor for this deviation from the standard.
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--
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-- o If you are about to simulate a large RAM e.g. 4M * 32 Bit, representing
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-- the RAM with a static array variable of 4 * 32 std_logic values uses a large
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-- amount of memory and may result in an out-of-memory error. A potential remedy
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-- for this is to use a dynamic data type, allocating memory for small blocks of
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-- RAM data (e.g. a single word) only if they are actually referenced during a
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-- simulation run. A version of the SRAM model with dynamic memory allocation
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-- shall be available at the same WWW-site were you obtained this file or at:
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-- http://tech-www.informatik.uni-hamburg.de/vhdl/models/sram/sram.html
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--
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--
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-- Bugs:
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--
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-- No severe bugs have been found so far. Please report any bugs:
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-- e-mail: klindwor@informatik.uni-hamburg.de
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--
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USE std.textio.all;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_unsigned.all;
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USE IEEE.std_logic_textio.all;
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ENTITY sram IS
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GENERIC (
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clear_on_power_up: boolean := FALSE; -- if TRUE, RAM is initialized with zeroes at start of simulation
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-- Clearing of RAM is carried out before download takes place
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download_on_power_up: boolean := TRUE; -- if TRUE, RAM is downloaded at start of simulation
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trace_ram_load: boolean := TRUE; -- Echoes the data downloaded to the RAM on the screen
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-- (included for debugging purposes)
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enable_nWE_only_control: boolean := TRUE; -- Read-/write access controlled by nWE only
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-- nOE may be kept active all the time
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-- Configuring RAM size
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size: INTEGER := 8; -- number of memory words
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adr_width: INTEGER := 3; -- number of address bits
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width: INTEGER := 8; -- number of bits per memory word
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-- READ-cycle timing parameters
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tAA_max: TIME := 20 NS; -- Address Access Time
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tOHA_min: TIME := 3 NS; -- Output Hold Time
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tACE_max: TIME := 20 NS; -- nCE/CE2 Access Time
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tDOE_max: TIME := 8 NS; -- nOE Access Time
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tLZOE_min: TIME := 0 NS; -- nOE to Low-Z Output
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tHZOE_max: TIME := 8 NS; -- OE to High-Z Output
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tLZCE_min: TIME := 3 NS; -- nCE/CE2 to Low-Z Output
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tHZCE_max: TIME := 10 NS; -- CE/nCE2 to High Z Output
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-- WRITE-cycle timing parameters
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tWC_min: TIME := 20 NS; -- Write Cycle Time
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tSCE_min: TIME := 18 NS; -- nCE/CE2 to Write End
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tAW_min: TIME := 15 NS; -- tAW Address Set-up Time to Write End
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tHA_min: TIME := 0 NS; -- tHA Address Hold from Write End
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tSA_min: TIME := 0 NS; -- Address Set-up Time
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tPWE_min: TIME := 13 NS; -- nWE Pulse Width
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tSD_min: TIME := 10 NS; -- Data Set-up to Write End
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tHD_min: TIME := 0 NS; -- Data Hold from Write End
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tHZWE_max: TIME := 10 NS; -- nWE Low to High-Z Output
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tLZWE_min: TIME := 0 NS -- nWE High to Low-Z Output
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);
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PORT (
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nCE: IN std_logic := '1'; -- low-active Chip-Enable of the SRAM device; defaults to '1' (inactive)
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nOE: IN std_logic := '1'; -- low-active Output-Enable of the SRAM device; defaults to '1' (inactive)
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nWE: IN std_logic := '1'; -- low-active Write-Enable of the SRAM device; defaults to '1' (inactive)
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A: IN std_logic_vector(adr_width-1 downto 0); -- address bus of the SRAM device
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D: INOUT std_logic_vector(width-1 downto 0); -- bidirectional data bus to/from the SRAM device
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CE2: IN std_logic := '1'; -- high-active Chip-Enable of the SRAM device; defaults to '1' (active)
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download: IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal downloads the data
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-- in file specified by download_filename to the RAM
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download_filename: IN string := "sram_load.dat"; -- name of the download source file
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-- Passing the filename via a port of type
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-- ********** string may cause a problem with some
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-- WATCH OUT! simulators. The string signal assigned
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-- ********** to the port at least should have the
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-- same length as the default value.
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dump: IN boolean := FALSE; -- A FALSE-to-TRUE transition on this signal dumps
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-- the current content of the memory to the file
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-- specified by dump_filename.
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dump_start: IN natural := 0; -- Written to the dump-file are the memory words from memory address
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dump_end: IN natural := size-1; -- dump_start to address dump_end (default: all addresses)
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dump_filename: IN string := "sram_dump.dat" -- name of the dump destination file
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-- (See note at port download_filename)
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);
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END sram;
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ARCHITECTURE behavior OF sram IS
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FUNCTION Check_For_Valid_Data (a: std_logic_vector) RETURN BOOLEAN IS
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VARIABLE result: BOOLEAN;
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BEGIN
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result := TRUE;
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FOR i IN a'RANGE LOOP
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result := (a(i) = '0') OR (a(i) = '1');
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IF NOT result THEN EXIT;
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END IF;
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END LOOP;
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RETURN result;
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END Check_For_Valid_Data;
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FUNCTION Check_For_Tristate (a: std_logic_vector) RETURN BOOLEAN IS
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VARIABLE result: BOOLEAN;
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BEGIN
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result := TRUE;
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FOR i IN a'RANGE LOOP
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result := (a(i) = 'Z');
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IF NOT result THEN EXIT;
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END IF;
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END LOOP;
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RETURN result;
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END Check_For_Tristate;
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SIGNAL tristate_vec: std_logic_vector(D'RANGE); -- constant all-Z vector for data bus D
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SIGNAL undef_vec: std_logic_vector(D'RANGE); -- constant all-X vector for data bus D
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SIGNAL undef_adr_vec: std_logic_vector(A'RANGE); -- constant all-X vector for address bus
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SIGNAL read_active: BOOLEAN := FALSE; -- Indicates whether the SRAM is sending on the D bus
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SIGNAL read_valid: BOOLEAN := FALSE; -- If TRUE, the data output by the RAM is valid
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SIGNAL read_data: std_logic_vector(D'RANGE); -- content of the memory location addressed by A
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SIGNAL do_write: std_logic := '0'; -- A '0'->'1' transition on this signal marks
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-- the moment when the data on D is stored in the
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-- addressed memory location
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SIGNAL adr_setup: std_logic_vector(A'RANGE); -- delayed value of A to model the Address Setup Time
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SIGNAL adr_hold: std_logic_vector(A'RANGE); -- delayed value of A to model the Address Hold Time
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SIGNAL valid_adr: std_logic_vector(A'RANGE); -- valid memory address derived from A after
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-- considering Address Setup and Hold Times
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BEGIN
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PROCESS BEGIN -- static assignments to the variable length busses'
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-- all-X and all-Z signal vectors
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FOR i IN D'RANGE LOOP
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tristate_vec(i) <= 'Z';
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undef_vec(i) <= 'X';
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END LOOP;
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FOR i IN A'RANGE LOOP
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undef_adr_vec(i) <= 'X';
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END LOOP;
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WAIT;
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END PROCESS;
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memory: PROCESS
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CONSTANT low_address: natural := 0;
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CONSTANT high_address: natural := size -1;
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TYPE memory_array IS
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ARRAY (natural RANGE low_address TO high_address) OF std_logic_vector(width-1 DOWNTO 0);
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VARIABLE mem: memory_array;
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VARIABLE address : natural;
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VARIABLE write_data: std_logic_vector(width-1 DOWNTO 0);
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PROCEDURE power_up (mem: inout memory_array; clear: boolean) IS
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VARIABLE init_value: std_logic;
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BEGIN
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IF clear THEN
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init_value := '0';
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write(output, string'("Initializing SRAM with zero ...") );
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ELSE
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init_value := 'X';
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END IF;
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FOR add IN low_address TO high_address LOOP
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FOR j IN (width-1) DOWNTO 0 LOOP
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mem(add)(j) := init_value;
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END LOOP;
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END LOOP;
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END power_up;
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PROCEDURE load (mem: INOUT memory_array; download_filename: IN string) IS
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FILE source : text IS IN download_filename;
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VARIABLE inline, outline : line;
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VARIABLE add: natural;
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VARIABLE c : character;
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VARIABLE source_line_nr: integer := 1;
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VARIABLE init_value: std_logic := 'U';
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BEGIN
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write(output, string'("Loading SRAM from file ") & download_filename & string'(" ... ") );
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WHILE NOT endfile(source) LOOP
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readline(source, inline);
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read(inline, add);
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read(inline, c);
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IF (c /= ' ') THEN
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write(outline, string'("Syntax error in file '"));
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write(outline, download_filename);
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write(outline, string'("', line "));
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write(outline, source_line_nr);
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writeline(output, outline);
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ASSERT FALSE
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REPORT "RAM loader aborted."
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SEVERITY FAILURE;
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END IF;
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FOR i IN (width -1) DOWNTO 0 LOOP
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read(inline, c);
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IF (c = '1') THEN
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mem(add)(i) := '1';
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ELSE
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IF (c /= '0') THEN
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write(outline, string'("-W- Invalid character '"));
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write(outline, c);
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write(outline, string'("' in Bitstring in '"));
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write(outline, download_filename);
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write(outline, '(');
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write(outline, source_line_nr);
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write(outline, string'(") is set to '0'"));
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writeline(output, outline);
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END IF;
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mem(add)(i) := '0';
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END IF;
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END LOOP;
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IF (trace_ram_load) THEN
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write(outline, string'("RAM["));
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write(outline, add);
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write(outline, string'("] := "));
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write(outline, mem(add));
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writeline(output, outline );
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END IF;
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source_line_nr := source_line_nr +1;
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END LOOP; -- WHILE
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END load; -- PROCEDURE
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PROCEDURE do_dump (mem: INOUT memory_array;
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dump_start, dump_end: IN natural;
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dump_filename: IN string) IS
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FILE dest : text IS OUT dump_filename;
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VARIABLE l : line;
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VARIABLE c : character;
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BEGIN
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IF (dump_start > dump_end) OR (dump_end >= size) THEN
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ASSERT FALSE
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REPORT "Invalid addresses for memory dump. Cancelled."
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SEVERITY ERROR;
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ELSE
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FOR add IN dump_start TO dump_end LOOP
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write(l, add);
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write(l, ' ');
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FOR i IN (width-1) downto 0 LOOP
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write(l, mem(add)(i));
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END LOOP;
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writeline(dest, l);
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END LOOP;
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END IF;
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END do_dump; -- PROCEDURE
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BEGIN
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power_up(mem, clear_on_power_up);
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IF download_on_power_up THEN
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load(mem, download_filename);
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END IF;
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LOOP
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IF do_write'EVENT and (do_write = '1') then
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IF NOT Check_For_Valid_Data(D) THEN
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IF D'EVENT AND Check_For_Valid_Data(D'DELAYED) THEN
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write(output, "-W- Data changes exactly at end-of-write to SRAM.");
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write_data := D'delayed;
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ELSE
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write(output, "-E- Data not valid at end-of-write to SRAM.");
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write_data := undef_vec;
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END IF;
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ELSIF NOT D'DELAYED(tHD_min)'STABLE(tSD_min) THEN
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write(output, "-E- tSD violation: Data input changes within setup-time at end-of-write to SRAM.");
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write_data := undef_vec;
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ELSIF NOT D'STABLE(tHD_min) THEN
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write(output, "-E- tHD violation: Data input changes within hold-time at end-of-write to SRAM.");
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write_data := undef_vec;
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ELSIF nWE'DELAYED(tHD_min)'STABLE(tPWE_min) THEN
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write(output, "-E- tPWE violation: Pulse width of nWE too short at SRAM.");
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write_data := undef_vec;
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ELSE write_data := D;
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END IF;
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mem(CONV_INTEGER(valid_adr)) := write_data;
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END IF;
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IF Check_For_Valid_Data(valid_adr) THEN
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read_data <= mem(CONV_INTEGER(valid_adr));
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ELSE
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read_data <= undef_vec;
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END IF;
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IF dump AND dump'EVENT THEN do_dump(mem, dump_start, dump_end, dump_filename);
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END IF;
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IF download AND download'EVENT THEN load(mem, download_filename);
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END IF;
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WAIT ON do_write, valid_adr, dump, download;
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END LOOP;
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END PROCESS memory;
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adr_setup <= TRANSPORT A AFTER tAA_max;
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adr_hold <= TRANSPORT A AFTER tOHA_min;
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valid_adr <= adr_setup WHEN Check_For_Valid_Data(adr_setup)
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AND (adr_setup = adr_hold)
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AND adr_hold'STABLE(tAA_max - tOHA_min) ELSE
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undef_adr_vec;
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read_active <= ( (nOE = '0') AND (nOE'DELAYED(tLZOE_min) = '0') AND nOE'STABLE(tLZOE_min)
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AND ((nWE = '1') OR (nWE'DELAYED(tHZWE_max) = '1'))
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AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tLZCE_min) AND CE2'STABLE(tLZCE_min))
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OR (read_active AND (nOE'DELAYED(tHZOE_max) = '0')
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AND (nWE'DELAYED(tHZWE_max) = '1')
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AND (nCE'DELAYED(tHZCE_max) = '0') AND (CE2'DELAYED(tHZCE_max) = '1'));
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read_valid <= ( (nOE = '0') AND nOE'STABLE(tDOE_max)
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AND (nWE = '1') AND (nWE'DELAYED(tHZWE_max) = '1')
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AND (nCE = '0') AND (CE2 = '1') AND nCE'STABLE(tACE_max) AND CE2'STABLE(tACE_max))
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OR (read_valid AND read_active);
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D <= read_data WHEN read_valid and read_active ELSE
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undef_vec WHEN not read_valid and read_active ELSE
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tristate_vec;
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PROCESS (nWE, nCE, CE2)
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BEGIN
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IF ((nCE = '1') OR (nWE = '1') OR (CE2 = '0'))
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AND (nCE'DELAYED = '0') AND (CE2'DELAYED = '1') AND (nWE'DELAYED = '0') -- End of Write
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THEN
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do_write <= '1' AFTER tHD_min;
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ELSE
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IF (Now > 10 NS) AND (nCE = '0') AND (CE2 = '1') AND (nWE = '0') -- Start of Write
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THEN
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ASSERT Check_For_Valid_Data(A)
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REPORT "Address not valid at start-of-write to RAM."
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SEVERITY FAILURE;
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ASSERT A'STABLE(tSA_min)
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REPORT "tSA violation: Address changed within setup-time at start-of-write to SRAM."
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SEVERITY ERROR;
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ASSERT enable_nWE_only_control OR ((nOE = '1') AND nOE'STABLE(tSA_min))
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REPORT "tSA violation: nOE not inactive at start-of-write to RAM."
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SEVERITY ERROR;
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END IF;
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do_write <= '0';
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END IF;
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END PROCESS;
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|
|
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|
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-- The following processes check for validity of the control signals at the
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|
-- SRAM interface. Removing them to speed up simulation will not affect the
|
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-- functionality of the SRAM model.
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PROCESS (A) -- Checks that an address change is allowed
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BEGIN
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IF (Now > 0 NS) THEN -- suppress obsolete error message at time 0
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ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
|
|
REPORT "Address not stable while write-to-SRAM active"
|
|
SEVERITY FAILURE;
|
|
|
|
ASSERT (nCE = '1') OR (CE2 = '0') OR (nWE = '1')
|
|
OR (nCE'DELAYED(tHA_min) = '1') OR (CE2'DELAYED(tHA_min) = '0')
|
|
OR (nWE'DELAYED(tHA_min) = '1')
|
|
REPORT "tHA violation: Address changed within hold-time at end-of-write to SRAM."
|
|
SEVERITY FAILURE;
|
|
END IF;
|
|
END PROCESS;
|
|
|
|
|
|
PROCESS (nOE, nWE, nCE, CE2) -- Checks that control signals at RAM are valid all the time
|
|
BEGIN
|
|
IF (Now > 0 NS) AND (nCE /= '1') AND (CE2 /= '0') THEN
|
|
IF (nCE = '0') AND (CE2 = '1') THEN
|
|
ASSERT (nWE = '0') OR (nWE = '1')
|
|
REPORT "Invalid nWE-signal at SRAM while nCE is active"
|
|
SEVERITY WARNING;
|
|
ELSE
|
|
IF (nCE /= '0') THEN
|
|
ASSERT (nOE = '1')
|
|
REPORT "Invalid nCE-signal at SRAM while nOE not inactive"
|
|
SEVERITY WARNING;
|
|
|
|
ASSERT (nWE = '1')
|
|
REPORT "Invalid nCE-signal at SRAM while nWE not inactive"
|
|
SEVERITY ERROR;
|
|
END IF;
|
|
IF (CE2 /= '1') THEN
|
|
ASSERT (nOE = '1')
|
|
REPORT "Invalid CE2-signal at SRAM while nOE not inactive"
|
|
SEVERITY WARNING;
|
|
|
|
ASSERT (nWE = '1')
|
|
REPORT "Invalid CE2-signal at SRAM while nWE not inactive"
|
|
SEVERITY ERROR;
|
|
END IF;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
|
|
END behavior;
|