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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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library std_developerskit ; -- used for to_string
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-- use std_developerskit.std_iopak.all;
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entity slave_tb is
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end;
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architecture rtl of slave_tb is
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constant CLK_FAST_PERIOD : time := 1 us / (14*7);
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constant CLK_PERIOD : time := 1 us / (14);
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constant CLK_CART_PERIOD : time := 1 us / (1.79*32);
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signal reset_n : std_logic;
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signal clk7x : std_logic;
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signal clk : std_logic;
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signal clk_cart : std_logic;
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signal EXT_SRAM_ADDR: std_logic_vector(19 downto 0);
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signal EXT_SRAM_DATA: std_logic_vector(7 downto 0);
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signal EXT_SRAM_CE: std_logic;
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signal EXT_SRAM_OE: std_logic;
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signal EXT_SRAM_WE: std_logic;
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signal CART_ADDR: std_logic_vector(12 downto 0);
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signal CART_DATA: std_logic_vector(7 downto 0);
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signal CART_RD5: std_logic;
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signal CART_RD4: std_logic;
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signal CART_S5: std_logic;
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signal CART_S4: std_logic;
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signal CART_PHI2: std_logic;
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signal CART_CTL: std_logic;
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signal CART_RW: std_logic;
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-- 65816 bus
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signal veronica_address : std_logic_vector(23 downto 0);
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signal veronica_read_data : std_logic_vector(7 downto 0);
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signal veronica_write_data : std_logic_vector(7 downto 0);
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signal veronica_w_n : std_logic;
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signal veronica_config_w_n : std_logic;
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-- 6502 bus
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signal atari_bus_request : std_logic;
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signal atari_address : std_logic_vector(12 downto 0);
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signal atari_data_bus : std_logic_vector(7 downto 0);
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signal atari_read_data : std_logic_vector(7 downto 0);
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signal atari_write_data : std_logic_vector(7 downto 0);
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signal atari_w_n : std_logic;
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signal atari_config_w_n : std_logic;
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signal atari_s4 : std_logic;
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signal atari_s5 : std_logic;
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signal atari_ctl : std_logic;
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-- address decode
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signal veronica_config_select : std_logic;
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signal veronica_sram_select : std_logic;
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signal veronica_sram_address: std_logic_vector(16 downto 0);
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signal atari_config_select : std_logic;
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signal atari_sram_select : std_logic;
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signal atari_sram_address: std_logic_vector(16 downto 0);
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-- veronica config
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signal veronica_window_address : std_logic;
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signal veronica_bank_half_select : std_logic;
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signal veronica_config_data : std_logic_vector(7 downto 0);
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-- atari config
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signal atari_banka_enable : std_logic;
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signal atari_bank8_enable : std_logic;
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signal atari_bank_half_select : std_logic;
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signal atari_config_data : std_logic_vector(7 downto 0);
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-- common config
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signal common_sem : std_logic;
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signal common_bank_select : std_logic;
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-- cart driving
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signal cart_bus_data_out : std_logic_vector(7 downto 0);
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signal cart_bus_drive : std_logic;
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-- sram driving
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signal sram_write_data : std_logic_vector(7 downto 0);
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signal sram_drive_data : std_logic;
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signal sram_read_data : std_logic_vector(7 downto 0);
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-- 6502 bus other side
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signal enable_179_early : std_logic;
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signal cart_request : std_logic;
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signal pbi_addr_out : std_logic_vector(15 downto 0);
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signal cart_data_write : std_logic_vector(7 downto 0);
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signal pbi_write_enable : std_logic;
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signal s4_n : std_logic;
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signal s5_n : std_logic;
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signal cctl_n : std_logic;
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signal cart_data_read : std_logic_vector(7 downto 0);
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signal cart_complete : std_logic;
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signal bus_data_in : std_logic_vector(7 downto 0);
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signal bus_data_out : std_logic_vector(7 downto 0);
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signal bus_data_oe : std_logic;
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signal bus_addr_out : std_logic_vector(15 downto 0);
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signal bus_addr_oe : std_logic;
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signal bus_write_n : std_logic;
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signal bus_s4_n : std_logic;
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signal bus_s5_n : std_logic;
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signal bus_cctl_n : std_logic;
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signal bus_control_oe : std_logic;
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begin
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p_clk_gen_a : process
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begin
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clk <= '1';
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wait for CLK_PERIOD/2;
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clk <= '0';
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wait for CLK_PERIOD - (CLK_PERIOD/2 );
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end process;
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p_clk_gen_b : process
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begin
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clk_cart <= '1';
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wait for CLK_CART_PERIOD/2;
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clk_cart <= '0';
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wait for CLK_CART_PERIOD - (CLK_CART_PERIOD/2 );
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end process;
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p_clk_gen_c : process
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begin
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clk7x <= '1';
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wait for CLK_FAST_PERIOD/2;
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clk7x <= '0';
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wait for CLK_FAST_PERIOD - (CLK_FAST_PERIOD/2 );
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end process;
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reset_n <= '0', '1' after 1000ns;
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process_enable : process
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begin
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '1'; -- HERE!
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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wait until clk_cart'event and clk_cart = '1';
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enable_179_early <= '0';
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end process;
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process_setup_sram : process
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begin
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cart_request <= '0';
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pbi_addr_out <= (others=>'0');
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cart_data_write <= (others=>'0');
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pbi_write_enable <= '0';
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s4_n <= '1';
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s5_n <= '1';
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cctl_n <= '1';
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wait for 3000ns;
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D402";
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cart_data_write <= x"65";
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pbi_write_enable <= '1';
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s4_n <= '0';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D513";
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cart_data_write <= x"56";
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pbi_write_enable <= '1';
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s5_n <= '0';
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s4_n <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '1';
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pbi_addr_out <= x"D402";
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cart_data_write <= x"65";
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pbi_write_enable <= '1';
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wait until enable_179_early'event and enable_179_early = '1';
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cart_request <= '0';
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wait for 100000000us;
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end process;
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glue3: entity work.slave_timing_6502
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port map
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(
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clk => clk,
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clk7x => clk7x,
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reset_n => reset_n,
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phi2 => CART_PHI2,
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bus_addr => CART_ADDR,
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bus_data => CART_DATA,
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bus_ctl_n => CART_CTL,
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bus_rw_n => CART_RW,
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bus_s4_n => CART_S4,
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bus_s5_n => CART_S5,
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bus_data_out => cart_bus_data_out,
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bus_drive => cart_bus_drive,
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s4_n => atari_s4,
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s5_n => atari_s5,
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ctl_n => atari_ctl,
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addr_in => atari_address,
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data_in => atari_write_data,
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data_out => atari_read_data,
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rw_n => atari_w_n,
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bus_request => atari_bus_request
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);
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CART_DATA <= cart_bus_data_out when cart_bus_drive='1' else (others=>'Z');
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atari_read_data <= x"12" when atari_bus_request='1' else (others=>'U');
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bus_adaptor : ENTITY work.timing6502
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GENERIC MAP
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(
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CYCLE_LENGTH => 32,
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CONTROl_BITS => 3
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)
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PORT MAP
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(
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CLK => clk_cart,
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RESET_N => reset_n,
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-- FPGA side
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ENABLE_179_EARLY =>enable_179_early,
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REQUEST => cart_request,
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ADDR_IN => pbi_addr_out,
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DATA_IN => cart_data_write,
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WRITE_IN => pbi_write_enable,
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CONTROL_N_IN => s4_n&s5_n&cctl_n,
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DATA_OUT => cart_data_read,
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COMPLETE => cart_complete,
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-- 6502 side
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BUS_DATA_IN => CART_DATA,
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BUS_PHI1 => open,
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BUS_PHI2 => CART_PHI2,
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BUS_SUBCYCLE => open,
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BUS_ADDR_OUT => bus_addr_out,
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BUS_ADDR_OE => bus_addr_oe,
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BUS_DATA_OUT => bus_data_out,
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BUS_DATA_OE => bus_data_oe,
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BUS_WRITE_N => CART_RW,
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BUS_CONTROL_N(2) => bus_s4_n,
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BUS_CONTROL_N(1) => bus_s5_n,
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BUS_CONTROL_N(0) => bus_cctl_n,
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BUS_CONTROL_OE => bus_control_oe
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);
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CART_ADDR <= bus_addr_out when bus_addr_oe='1' else (others=>'Z');
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CART_DATA <= bus_data_out when bus_data_oe='1' else (others=>'Z');
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CART_S4 <= bus_s4_n when bus_control_oe='1' else 'Z';
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CART_S5 <= bus_s5_n when bus_control_oe='1' else 'Z';
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CART_CTL <= bus_cctl_n when bus_control_oe='1' else 'Z';
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end rtl;
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